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update umctl2's setting based on phy training CDD value
to workaround the rank-to-rank space issue.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 8cd4fa6dfff74b190294141bdc22634a7cb40a30)
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the dfiphymaster setting need to be save/restore to make sure
it aligned with the initial config.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit e9dfde639db8593aa12d779f1990c8bb276e711c)
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the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit 57bf8a00a74f12671cb38863bbc3606b3834f195)
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the bitfield of active_ranks in MSTR is defined as below.
Correct the rank num get in dram_info.
0x01: one rank;
0x11: two rank;
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
(cherry picked from commit bc9bc03f38fecbf5a2e4d938ed6f45fb3ec0b574)
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In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the i.MX8MP workaround for wait mode just for Alpha
release, this patch will be dropped in the future.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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move the gpc reg offset, bit define & macro to a separate header
file for code reuse.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Enable DRAM DVFS support on i.MX8MQ.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
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Enable dram retention support on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the dram retention flow for i.MX8M SoC family.
Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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