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APB Write data corruption following MRCTRL0.mr_wr=1 while
hardware-driven MR access is occurring
When performing a software driven MR access, the following
sequence must be done automatically before performing other
APB register accesses:
1. Set MRCTRL0.mr_wr=1
2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2)
3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2)
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5)
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This is log is just for debug purpose only. Change the
ddr4 dvfs debug log print level to disable this log print
by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
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the DDR3L & DDR4 can share same piece of code of DVFS, so update
the ddr4 dvfs to support DDR3L too.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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In step12, remove the while loop waiting to align
with the ddr4 dvfs flow on imx_2.0.y.
Tested-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
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