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2020-05-11MLK-23969 imx: Update SCFW API message type according to latest SCFWAnson Huang
The SCFW commit 3e500fb26979 ("SCF-621: Change pad width in sc_rm_is_pad_owned() RPC.") changes pad width in sc_rm_is_pad_owned() RPC, update it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit 9b8cf9247f1ba85b520f93cae0bb421feb12e76f)
2020-04-07MLK-23727 imx8mp/n: support stop M7Peng Fan
Support stop M7 with SIP call. Per IC team, to rekick M7 need follow steps. If M7 already in WFI, perform below steps. a) Set [0x303A_002C].0=0 [ request SLEEPHOLDREQn ] b) Wait [0x303A_00EC].1 = 0 [ wait SLEEPHOLDACKn ] c) Set GPR.CPUWAIT=1 d) Set [0x303A_002C].0=1 [ de-assert SLEEPHOLDREQn ] e) Set SRC_M7_RCR[3:0] = 0xE0 [ reset M7 core/plat ] f) Wait SRC_M7_RCR[3:0] = 0x8 g) Init TCM or DDR h) Set GPR.INITVTOR i) Set GPR.CPUWAIT=0, M7 starting running Add a timeout check, if timeout, still perform force reset, in this way no need to rely on M7 team's image wfi support ready. Return a1,a2 to caller to check timeout or reset fail. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-03-27plat: imx8mp: Add basic support for imx8mpJacky Bai
Add the basic support for i.MX8MP. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-03-27TEE-532-7 plat: imx8dx: Add support for BL32Silvano di Ninno
8DX and 8QX share the same die, so will reuse the same implementation Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit bb209a0b4ccca2aa4a3a887f9606dc4a3d294adf)
2020-03-10plat: imx8dxl: Add iMX8DXL supportTeo Hall
Add support for new SoC i.MX8DXL Signed-off-by: Teo Hall <teo.hall@nxp.com> (cherry picked from a7a008da03cd08cae3387c428ad8145fb1fae354)
2020-03-09imx8q: Fix build errorsJi Luo
Build break due to result of ‘1 << 31’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=]. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2020-03-07Enable CPU, FP, L2 retention counters to 64 cyclesNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2020-02-09plat: imx8mq: Add the NOC sip handler on imx8mqJacky Bai
Add the NOC QoS setting SiP handler on imx8mq. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add the src handler for m4/m7 core boot supportJacky Bai
Add the SRC SiP handler for M4/M7 boot support on i.MX8M SoC. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8m: Add hab suport on imx8m SoC familyJacky Bai
Add the HAB secure boot support for the i.MX8M SoC family. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Enable dram dvfs support on imx8mqJacky Bai
Enable DRAM DVFS support on i.MX8MQ. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-02-09plat: imx8mq: Add workaround code for ERR11171 on imx8mqJacky Bai
This new workaround takes advantage of the per core IMR registers in GPC in order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register (which now remains always set), so it can only wake up one core at the time. Also, this entire workaround has now been moved here in TF-A, allowing the kernel side to be minimal. Another advantage this workaround brings is the removal of the 50us delay (which was necessary before in gic_raise_softirq in kernel) by allowing the core that is waking up to mask his own IRQ0 in the suspend finish callback. One important change here is the way the cores are woken up in dram_dvfs_handler. Since the wake up mechanism has changed from asserting the 12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then masking/unmasking the IMR1 1st bit for each independent core, we need to use the imx_gpc_core_wake to wake up the cores. Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel (gic_raise_softirq), since the new cpuidle workaround does not need it in order to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed in order to delay the affinity info OFF for the dying core. This is something that needs further investigation. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2020-01-03plat: imx8m: Add the PU power domain support on imx8mm/mnJacky Bai
Add the PU power domain support for imx8mm/mn. Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-12-13MLK-20986 imx8: Not protect OCRAM for rev AYe Li
On iMX8 Rev A the OCRAM is used to pass over ROM info, and u-boot needs to access it. So we can't assign the OCRAM to ATF partition. This will cause boot hang. Rev A does not support SPL, so it is ok to not protect the OCRAM. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit c9a168bfd16e06b4d6b9f94185910023e4923cf2)
2019-12-13plat:imx8qm/imx8qxp: Update SCFW APIRanjani Vaidyanathan
Sync SCFW API to commit b3c575a62b0e2 SCFW API version 16 Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
2019-12-13MLK-23071: Update LPUART settings for correct behaviorTeo Hall
Update flags for expected behavior in ATF Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-12-13plat: imx8m: Add the ddr frequency change support for imx8m familyJacky Bai
Add the DDR frequency change support. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
2019-12-13imx: Fix platform config name to support partition rebootAnson Huang
For platform CONFIGs, platform name should use lower case. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13plat: imx: Correct the SGIs that used for secure interruptJacky Bai
Normally, SGI6 & SGI7 is used by non-secure world, these two SGIs should not be reserved for secure interrupt purpose. On i.MX8M platform, SGI8 is used for secure group0 IPI for DDR DVFS, So update the code to reserve SGI8 for secure world. Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a Signed-off-by: Jacky Bai <ping.bai@nxp.com>
2019-12-13plat: imx: Add pwr_domain_pwr_down_wfi callback for i.MX8QXAnson Huang
Add pwr_domain_pwr_down_wfi callback for i.MX8QX. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13plat: imx8qm/imx8qxp: Update SCFW APIAnson Huang
Sync SCFW API to commit 6dcd0242ae Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13plat: imx: Enable L2 ECC & parity for A72 clusterAnson Huang
As per design team's suggestion, L2 cache's ECC & parity should be enabled for A72 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13Fix A72 L2 DATA latency settings.Nitin Garg
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13imx: add system_reset2 support for i.MX8QM/i.MX8QXAnson Huang
Add system_reset2 support for i.MX8QM/i.MX8QX to support WARM/COLD/BOARD reset. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13plat: imx8qm/imx8qxp: Add MU flag check for partition rebootTeo Hall
Test if a partition reboot has taken place with the MU interrupt bit. Check before returning the entrypoint Signed-off-by: Teo Hall <teo.hall@nxp.com>
2019-12-13Add NXP's i.MX8 SoCs system controller console supportAnson Huang
NXP's i.MX8 SoCs with system controller inside support outputting debug message to system controller's console via calling SCFW API, since TF-A shares debug console with Linux kernel which will have confliction if Linux kernel and TF-A's console are both enabled, this patch adds support for switching TF-A debug console to system controller to easy TF-A debug. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-11-22Add NXP's SoCs partition reboot support.Anson Huang
For NXP's SoCs with system controller inside, partition reboot is supported in SCFW, change the system reset API from board reset to partition reboot, so each partition can reboot independently. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-11-22plat: imx: Add WDOG functions SIP supportAnson Huang
Add WDOG functions SIP support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-08-01Replace __ASSEMBLY__ with compiler-builtin __ASSEMBLER__Julius Werner
NOTE: __ASSEMBLY__ macro is now deprecated in favor of __ASSEMBLER__. All common C compilers predefine a macro called __ASSEMBLER__ when preprocessing a .S file. There is no reason for TF-A to define it's own __ASSEMBLY__ macro for this purpose instead. To unify code with the export headers (which use __ASSEMBLER__ to avoid one extra dependency), let's deprecate __ASSEMBLY__ and switch the code base over to the predefined standard. Change-Id: Id7d0ec8cf330195da80499c68562b65cb5ab7417 Signed-off-by: Julius Werner <jwerner@chromium.org>
2019-07-26Merge changes from topic "jun-add-imx7-pico" into integrationSoby Mathew
* changes: plat: imx7: Add PicoPi iMX7D basic support plat: imx7: refactor code for reuse
2019-07-17plat: imx7: Add PicoPi iMX7D basic supportJun Nie
The PicoPi iMX7D is a 2 board development board consisting of a System-on-Module and a carrier baseboard and optimized for the Internet-of-Things (IoT). This patch add basic support to this board. Signed-off-by: Jun Nie <jun.nie@linaro.org> Reviewed-by: Louis Mayencourt <louis.mayencourt@arm.com> Change-Id: I009d85819c4f73b7063aab73d0f6ee74e6ef3fc4
2019-07-17plat: imx7: refactor code for reuseJun Nie
For the iMX7 SOCs, part of the code for platform setup implementation can be reused and made common for all these SoCs. This patch extracts the common part for reuse. Signed-off-by: Jun Nie <jun.nie@linaro.org> Change-Id: I42fd4167e6903416df96a0159a046abf3896e878
2019-07-12Update imx platform to not rely on undefined overflow behaviourJustin Chadwell
This consists of ensuring that the left operand of each shift is unsigned when the operation might overflow into the sign bit. Change-Id: Ia0a10b4a30e63c0cbf1d0f8dfe5768e0a93ae1c7 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-05-20imx8: Replace PLAT_IMX8* with automatic PLAT_imx8*Leonard Crestez
Platform defines are already provided by the build system so let's not duplicate them. Change-Id: Icf1ea76c3c3213e27b447c95e2b22b961fa7693e Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-05-20plat: imx8mq: Implement IMX_SIP_GET_SOC_INFOLeonard Crestez
The manual documents that 0x3036006c should contains the soc revision for imx8mq but this always reports A0. Work around this by parsing the ROM header and checking if OCOTP register 0x40 is stuck at 0xff0055aa. Determining this inside TF-A makes life easier for OS, see for example this linux discussion: https://lkml.org/lkml/2019/5/3/465 The soc revision can also be useful inside TF-A itself, for example for the non-upstream DDR DVFS "busfreq" feature is affected by 8mq erratas. The clock for OCOTP block can be disabled by OS so only initialize soc revision once at boot time. Change-Id: I9ca3f27840229ce8a28b53870e44da29f63c73aa Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-05-09plat: imx8m: Implement IMX_SIP_BUILDINFOLeonard Crestez
The IMX_SIP_BUILDINFO call was implemented for imx8qm and imx8qx but it's also applicable to imx8m. This fixes U-Boot not printing commit hash on 8m with upstream TF-A. Change-Id: Idcfd9729eaaccf329c24e241da325f1f6cd3c880 Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
2019-04-03Makefile: remove extra include paths in INCLUDESAmbroise Vincent
Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-04-03Console: remove deprecated finish_console_registerAmbroise Vincent
The old version of the macro is deprecated. Commit cc5859ca19ff ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-03-01imx: make sure GIC redistributor is awake before initializationAnson Huang
GICR_WAKER.ProcessorSleep can only be set to zero when: — GICR_WAKER.Sleep bit[0] == 0. — GICR_WAKER.Quiescent bit[31] == 0. On some platforms, when system reboot with GIC in sleep mode but with power ON, such as on NXP's i.MX8QM, Linux kernel enters suspend but could be requested to reboot, and GIC is in sleep mode and it is inside a power domain which is ON in this scenario, when CPU reset, the GIC driver trys to set CORE's redistributor interface to awake, with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] both set, the ProcessorSleep bit[1] will never be clear and cause system hang. This patch makes sure GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31] are both zeor before clearing ProcessorSleep bit[1]. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-02-12imx: warp7: Migrate to MULTI_CONSOLE_APIYing-Chun Liu (PaulLiu)
This commit migrates to MULTI_CONSOLE_API for IMX Warp7 board. We also rename the functions in imx_uart driver to more specific one. Signed-off-by: Ying-Chun Liu (PaulLiu) <paulliu@debian.org>
2019-01-29imx: power optimization for i.mx8qmAnson Huang
Current implementation of i.MX8QM power management related features does NOT optimize power number, all system resources like CCI, DDR, and A cluster etc. are kept in STBY mode (powered ON) when system suspend or CPU hotplug. To lower the power number, OFF mode should be adopted for those system resources whenever they can be OFF, A cluster will be OFF if the CPUs in the cluster are all off line, DDR/MU/DB can be OFF if system suspend, IRQ steer can be OFF if the wakeup source is belonged to system controller partition, so wakeup source runtime check is used to determine if IRQ steer can be OFF before system suspend. If resources are powered off for suspend, they should be restored properly after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-18imx: add i.MX8 SoCs build info SIP(silicon provider) service supportAnson Huang
This patch adds NXP i.MX8 SoCs' build info SIP support for easy debug. With this function enabled, TF-A's commit hash can be showed in u-boot debug console when booting up, when there is any issue which could be related to TF-A, users can use the commit hash value to easily identify which commit introduces the issue. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-18imx: add i.MX8 SoCs thermal alarm SIP(silicon provider) service supportAnson Huang
For NXP's i.MX8 SoCs with system controller inside, thermal sensors are maintained by SCFW, Linux needs to call SMC to trap to TF-A for thermal alarm operation etc. by calling SCFW API. This patch adds temperature alarm SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-18imx: add i.MX8 SoCs OTP SIP(silicon provider) service supportAnson Huang
For NXP's i.MX8 SoCs with system controller inside, OTP is maintained by SCFW, Linux needs to call SMC to trap to TF-A for OTP read/write etc. operations by calling SCFW API. This patch adds OTP SIP service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-18imx: support for i.MX8 SoCs misc IPCAnson Huang
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of misc functions like temperature alarm, dma etc., other Cortex-A clusters can send out command via MU (Message Unit) to system controller for misc operation etc.. This patch adds misc IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-18imx: add wakeup source SIP runtime service supportAnson Huang
On i.MX8QM/i.MX8QX with system controller inside, the wakeup source is managed in SCFW(system controller firmware), if the wakeup source is belonged to system controller partition, then before Linux suspend, the wakeup source should be set to SC_PM_WAKE_SRC_SCU, and if the wakeup source is belonged to Cortex-A partition, the wakeup source should be set to SC_PM_WAKE_SRC_IRQSTEER, so need to add wakeup source SIP runtime service to get Linux kernel's wakeup source and set the correct wakeup source for system controller. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-17imx: add cpu-freq SIP runtime service supportAnson Huang
On i.MX8QM/i.MX8QX with system controller inside, the CPU's clock rate is managed by SCFW(system controller firmware) and can ONLY be changed from secure world, so SIP runtime service is needed for setting CPU's clock rate, this patch adds cpu-freq SIP runtime service support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-17imx: add imx8qm/imx8qx SRTC SIP runtime service supportAnson Huang
On i.MX8QM/i.MX8QX with system controller inside, the SRTC is managed by SCFW(system controller firmware) and some functions like setting SRTC's time etc. can ONLY be requested from secure world, so SIP runtime service is needed for such kind of operations, this patch adds SRTC SIP runtime service support for i.MX8QM and i.MX8QX. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-17Support for NXP's i.MX8 SoCs timer IPCAnson Huang
NXP's i.MX8 SoCs have system controller (M4 core) which takes control of timer management, including watchdog, srtc and system counter etc., other clusters like Cortex-A35 can send out command via MU (Message Unit) to system controller for timer operation. This patch adds timer IPC(inter-processor communication) support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-01-15imx: make imx uart work for debug modeAnson Huang
With DEBUG_CONSOLE enabled, build will fail for imx8mq platform: ./build/imx8mq/release/bl31/imx8mq_bl31_setup.o: In function `bl31_early_platform_setup2': imx8mq_bl31_setup.c:(.text.bl31_early_platform_setup2+0x40): undefined reference to `console_uart_register' Makefile:741: recipe for target 'build/imx8mq/release/bl31/bl31.elf' failed make: *** [build/imx8mq/release/bl31/bl31.elf] Error 1 Besides, the .console_flush callback needs to be added to avoid panic when debug mode is enabled, since the console_flush() will call it without checking whether the function callback is valid. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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