Age | Commit message (Collapse) | Author |
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setup
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
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Fix Coverity CID 5209712: Uninitialized scalar variable (UNINIT)
issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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fix Coverity: CID 5243766: Uninitialized scalar variable (UNINIT)
issue.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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If no valid dram info to copy from DRAM, skip
copy the dram info.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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refact the dram low power related code to make it more
friendly for different dram config or different board.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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The RFSHCTL3.refresh_mode should be set normal mode if we
want to disable auto refresh mode.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Update the DDR4 DVFS flow
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add ddr4 retention flow for imx8m.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add support for enabling output debug message to SC
console, SC_CONSOLE is used to enable/disable it.
Example log output on SC console as below:
*** Debug Monitor ***
>$ NOTICE: smc_fid is c2000003
imx_pwr_domain_on cluster_id 0, cpu_id 1
cluster:0 core:1 is on
imx_pwr_domain_on cluster_id 0, cpu_id 2
cluster:0 core:2 is on
imx_pwr_domain_on cluster_id 0, cpu_id 3
cluster:0 core:3 is on
imx_pwr_domain_on cluster_id 1, cpu_id 0
cluster:1 core:0 is on
imx_pwr_domain_on cluster_id 1, cpu_id 1
cluster:1 core:1 is on
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add FSL_SIP_MISC_SET_TEMP support for setting thermal
alarm function.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Read the mode register setting from the DDRC, then we can
make the DVFS flow more indepent from the actual DDR config.
Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is
being used by u-boot. This is why u-boot crashes.
Changing the peripherals to protect, instead of gpio4 and 5, use csu
and rdc registers instead.
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
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Add NOC configuration entry for all the module.
Kernel can configure the noc priority through this entry.
Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
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imx_v2018.03 u-boot uses ROM's APIs: check_target and failsafe. So for iMX8M
platforms, we have to implement the sip calls and use ATF to call them when
u-boot running at non-secure world.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The DRAM APB bus clock rate is wrong before and after DVFS.
The register offset for APB bus clock is wrong, so fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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add LPDDR4 DVFS support on imx8mm.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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All the DRAM timing related config is saved by SPL in OCRAM_S,
so no need to do save for these configs in ATF anymore.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Switch to MULTI_CONSOLE_API to make debug UART work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Switch to MULTI_CONSOLE_API to make debug UART work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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skip init the dram info if the ddr type is DDR4,
support for it will be added later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add SIP service for OTP reading/writing for use
in u-boot
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Update API based on following commit:
commit 24fa33d2f95707e739f01cc04d38a62bec707ceb
Author: Chuck Cannon <chuck.cannon@nxp.com>
Date: Thu Jun 28 15:00:03 2018 -0500
SCF-105: Add disclaimer to docs.
Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com>
For use of the misc otp service
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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SC_R_IRQSTR_SCU2 can be OFF in system suspend if there
is no wakeup irq enabled from non-secure OS partion.
Add wakeup source check to decide if turning off
SC_R_IRQSTR_SCU2 or NOT when suspend.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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When GIC is power down, all the GIC state will be lost. All
the redistributor's state need save/resotre. Additionally,
the redistributor's restore need to be done after distributor
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add MU power off support for suspend, it needs
to be re-initialized after system resume.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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re-design the dram power management code to make it more
common for all i.MX8M SOCs. code need to refact and optimize
to make more better. Using this common code on i.MX8MM first,
for i.MX8MQ, will move to this later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
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i.MX8MM is a new soc of the i.MX8M family, this patch
add the basic support for i.MX8MM. further code optimization
needed. WAIT mode support is currently disabled, will be enabled
later.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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As the i.MX8MM and i.MX8MQ share the same hab file, move it
to common/imx8m, make it reusable for all i.MX8M SOCs.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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clean up the license identifier with short SPDX short identifier.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Use MU0 to comply with boot image usage of MU0
Also power on and pass MU1 for OS/Hypervisor
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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The GICv3 save/restore is necessary when GIC is going
to power off. the save/restore is common for all imx8
platform, so make it common for imx8.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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The SCFW API is updated based on below commit in SCFW:
commit 433c7fb773e3a5853e2744ff1f958bb225cd338a
Author: Chuck Cannon <chuck.cannon@nxp.com>
Date: Tue Apr 17 16:09:56 2018 -0500
Only default start CPUs for EMUL, SIMU, and test builds.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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"
commit 97b8a6eed4eee19ec8a60dedfffc2f5f3d8933c5
Author: Chuck Cannon <chuck.cannon@freescale.com>
Date: Tue Feb 6 08:54:16 2018 -0600
Add unique ID API call. Required to get info needed for SECO fuse
programming. Added info command to DM.
"
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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It is possible for multiple cores to do attempt RPC calls and without
locking this can result in corrupt messages on the SCFW side. This is
particularly visible with cpuidle.
This needs to be a bakery_lock because on the wakeup path
psci_cpu_suspend_finish calls the platform's pwr_domain_suspend_finish
before enabling the data cache.
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Anson Huang <anson.huang@nxp.com>
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Export build info for all i.mx8
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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On i.MX8MQ, NOC may need different settings for different
use cases, so add SIP for NOC settings.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Since the HAB only works in secure mode. The BL33 runs at EL2 non-secure can't
intialize the HAB successfully. So add the SIP call for these HAB interfaces,
BL33 will trap to ATF to run the HAB.
The HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to
authenticate image. Add these relevant memory region to MMU. Also extend the
stack size of each core to avoid stack overflow by HAB.
Signed-off-by: Ye Li <ye.li@nxp.com>
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Add power off interface for Linux. Currently poweroff the whole board,may
change to poweroff partition if necessary.
sync with the below scfw commit:
commit 0e1f8aa5d6c6a6d9b8c05d5a84bbd613b301d367
Author: Chuck Cannon <chuck.cannon@freescale.com>
Date: Tue Nov 28 13:56:29 2017 -0600
Use SC_R_BOARD_R1 to control the base board reset.
Signed-off-by: Chuck Cannon <chuck.cannon@freescale.com>
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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"commit 0245582bf4a58289e25c59fb0befe84923ca6742
Author: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
Date: Fri Nov 17 13:43:30 2017 -0600
Fix bug in system interface PM code.
Also ensure that DB/DBLOGIC is powered up before MU.
"
Signed-off-by: Ranjani Vaidyanathan <Ranjani.Vaidyanathan@nxp.com>
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Add watchdog pretimeout/status interfaces to sync with scfw.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Refact the PSCI related code. Enable cpuidle support
on i.MX8MQ for CPU idle support.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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i.MX8MQ does NOT update revision info in ANATOP_DIGPROG
register, so the revision info needs to read from ROM,
for security reason, this needs to be done in ATF, so
add this SIP support for kernel.
The A0 chip's ROM version is located at 0x800, and B0
chip is located at 0x83c.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add src sip to handle M4 boot and status check
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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When changing the DDR frequency, the DDRC will block
AXI access, so the code for changing the frequency need
to be run on OCRAM not make sure no DDR access at this stage.
the DDR frequency change request is from EL1 linux kernel side,
we use the SiP service call to trap the DDR frequency change operation
from linux kernel to ATF.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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To support virtual watchdog driver in Linux, add those watchdog functions
to call scfw interface in ATF.
Signed-off-by: Robin Gong <yibin.gong@nxp.com>
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Add SCFW APIs to support suspend/resume with all CPUs
power down.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Replace all GPL with BSD identifier.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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