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The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous
offset is incorrect, so actually ARM core is NOT powered
down and the power leakage is very high.
With this fix, each ARM core's leakage is about 25mA@0.9V.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW
power up/down. prevous bits assignment is wrong, so
fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Linux kernel will issue cpu-freq scale via SIP, ATF
calls SCFW API to finish the CPU frequency scale.
Move SIP service code from i.mx8mq to common place for
all i.mx SoCs.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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- USB PHY reset bit in SRC needs to be clear before
doing USB PHY power gating in GPC, only needs to
do once;
- Need to handle GPC_PU_PWRHSK during power up/down;
- Enable GPC pu power gate support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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As there are too many difference between each PU's power
on/off flow, here enable all PUs power until all modules'
power on/off function ready and tested, then we will enable
this PU PGC feature.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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the PCIE1 and PCIE2 share the same reset signal, if PCIE2 is power down,
PCIE1 will also be power down, so when we need to power up PCIE1, the PCIE2
need to power up too, only PCIE1 is power down, the PCIE2 power domain can
be power down too
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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No need to enable all PU power during boot up, module driver
will enable their power domain as needed.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Set the MPROTx and OPACRx in AIPS4 configuration registers to allow user mode
and non-supervisor privilege level to access.
Signed-off-by: Ye Li <ye.li@nxp.com>
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The power domain id does NOT equal to the register bit
offset, so need to do a mapping here.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add hardware power down for all power domains. Make
imx_gpc_set_m_core_pgc usable for all MIX and PU PGC.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Need to mask all M4 IRQ and override all PLLs/OSC
before entering DSM mode, but due to DRAM self-refresh
NOT ready, non-fast wakeup mode is NOT working, so
we still use fast wakeup mode, which means DSM mode
by default is NOT entered.
After DRAM self-refresh is added, we will switch
to non-fast wakeup mode to make DSM work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Move TZC EN into SPL, and add check in ATF.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add SNVS mapping to avoid system off failure.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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enable tzc380 for i.mx8mq
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Change back BL31_LIMIT to 0x40020000,
because TZC380 could not support 4K aligned address.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add console init
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Add system off support, linux kernel can issue
"poweroff" to power down system.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add wdog reset support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
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Enable the non-privilege access for AIPS address space.
Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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Add basic support for i.MX8MQ.
1. SMP support is ok.
2. basic suspend/resume support is ok.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
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