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path: root/plat/freescale/imx8mq/gpc.c
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2017-09-19freescale: replace all GPL with BSD identifier.imx_4.9.51_imx8_beta1Anson Huang
Replace all GPL with BSD identifier. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-09-02imx8mq: gpc: correct ARM power down request register offsetAnson Huang
The GPC_CPU_PGC_SW_PDN_REQ offset should be 0xfc, previous offset is incorrect, so actually ARM core is NOT powered down and the power leakage is very high. With this fix, each ARM core's leakage is about 25mA@0.9V. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-08-28fix sw pup/pdn issue on imx8mqBai Ping
The bits[3:0] of CPU_PGC_PUP/PDN_TRG use core's SW power up/down. prevous bits assignment is wrong, so fix it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-08-17imx8mq: enable PU power domainAnson Huang
- USB PHY reset bit in SRC needs to be clear before doing USB PHY power gating in GPC, only needs to do once; - Need to handle GPC_PU_PWRHSK during power up/down; - Enable GPC pu power gate support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-08-04imx8mq: enable all PUs power until all PUs power on/off function readyAnson Huang
As there are too many difference between each PU's power on/off flow, here enable all PUs power until all modules' power on/off function ready and tested, then we will enable this PU PGC feature. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-08-02imx8mq: fix the pcie power domain dependencyBai Ping
the PCIE1 and PCIE2 share the same reset signal, if PCIE2 is power down, PCIE1 will also be power down, so when we need to power up PCIE1, the PCIE2 need to power up too, only PCIE1 is power down, the PCIE2 power domain can be power down too Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-26imx8mq: do NOT enable all PU power during boot upAnson Huang
No need to enable all PU power during boot up, module driver will enable their power domain as needed. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-19imx8mq: gpc: power domain id needs to be mapped to register bit offsetAnson Huang
The power domain id does NOT equal to the register bit offset, so need to do a mapping here. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-19imx8mq: gpc: add hardware power down for power domainAnson Huang
Add hardware power down for all power domains. Make imx_gpc_set_m_core_pgc usable for all MIX and PU PGC. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-14imx8mq: gpc: mask m4 irq and override PLLs for dsmAnson Huang
Need to mask all M4 IRQ and override all PLLs/OSC before entering DSM mode, but due to DRAM self-refresh NOT ready, non-fast wakeup mode is NOT working, so we still use fast wakeup mode, which means DSM mode by default is NOT entered. After DRAM self-refresh is added, we will switch to non-fast wakeup mode to make DSM work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12i.mx8mq: Add basic support for i.mx8mqBai Ping
Add basic support for i.MX8MQ. 1. SMP support is ok. 2. basic suspend/resume support is ok. Signed-off-by: Bai Ping <ping.bai@nxp.com>