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2017-06-28Use CryptoCell to set/get NVcounters and ROTPKSoby Mathew
This patch implements the platform APIs plat_get_rotpk_info, plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM APIs when ARM_CRYPTOCELL_INT is set. Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28ARM plat changes to enable CryptoCell integrationSoby Mathew
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53danh-arm
Apply workarounds for A53 Cat A Errata 835769 and 843419
2017-06-26juno: Invalidate all caches before warm reset to AArch32 state.Dimitris Papastamos
On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-26juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot valueDimitris Papastamos
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-22Apply workarounds for A53 Cat A Errata 835769 and 843419Douglas Raillard
These errata are only applicable to AArch64 state. See the errata notice for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419. Enable both of them for Juno. Apply the 835769 workaround as following: * Compile with -mfix-cortex-a53-835769 * Link with --fix-cortex-a53-835769 Apply the 843419 workaround as following: * Link with --fix-cortex-a53-843419 The erratum 843419 workaround can lead the linker to create new sections suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the linker to create new "*.stub" sections with no particular alignment. Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for architecture-specific linker options. Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-20juno: Fix AArch32 buildDimitris Papastamos
Commit 6de8b24f52cf2bd74adefbaa86dd2a0676c3eaa2 broke Juno AArch32 build. Change-Id: Ied70d9becb86e53ccb46a2e3245e2a551d1bf701 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20sp_min: Implement `sp_min_plat_runtime_setup()`Dimitris Papastamos
On ARM platforms before exiting from SP_MIN ensure that the default console is switched to the runtime serial port. Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-16Merge pull request #953 from vwadekar/tegra-misra-fixes-v1davidcunado-arm
Tegra misra fixes v1
2017-06-16Merge pull request #986 from jagadeeshujja/jagujj/fix-get-power-statedavidcunado-arm
CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is set
2017-06-15CSS:Fix scpi "get_power_state" when ARM_PLAT_MT is setjagadeesh ujja
The ARM_PLAT_MT bit enables the support for MT bit in MPIDR format. This means that the level 0 affinity represents the thread and CPU / Cluster levels are at affinity level 1 and 2 respectively. This was not catered for in the scpi 'css_scp_get_power_state, API. Since the SCPI driver can only cater for single threaded CPUs, this patch fixes the problem by catering for this shift by effectively ignoring the Thread (level 0) affinity level. Change-Id: If44f55c9fb2773c8d3f8a9bbcf5420a6f7409dfe Signed-off-by: jagadeesh ujja <jagadeesh.ujja@arm.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-09Fix coverity error in CSS SCMI driverSoby Mathew
Change-Id: Ia7d731f429e452e4bc9f9a553d7105b6394c621c Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-05Merge pull request #963 from soby-mathew/sm/scmi_devdanh-arm
Add SCMI power domain and system power protocol support
2017-06-05Merge pull request #961 from jeenu-arm/gic-600danh-arm
Introduce ARM GIC-600 driver
2017-06-05Add SCMI support for Juno platformSoby Mathew
This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_map` array. Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-05CSS: Add SCMI driver for SCPSoby Mathew
This patch adds the SCMI driver for communicating with SCP. The power domain management and system power management protocol of the SCMI specification[1] is implemented in the driver. The SCP power management abstraction layer for SCMI for CSS power management is also added. A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI driver over SCPI. [1] ARM System Control and Management Interface v1.0 (SCMI) Document number: ARM DEN 0056A Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-01Introduce ARM GIC-600 driverJeenu Viswambharan
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-06-01Add support for Cortex-A75 and Cortex-A55 CPUsDavid Wang
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-30Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memorydavidcunado-arm
Reduce code size when building with Trusted Board Boot enabled
2017-05-24plat/arm: Compile out impossible conditional for AArch32dp-arm
Since ARM_DRAM2_BASE is above the 32-bit limit, the condition is always false. Wrap this condition in an ifndef to avoid warnings during compilation. Change-Id: Ideabb6c65de6c62474ed03eb29df4b049d5316be Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Remove plat_match_rotpk referencedp-arm
This function was removed long ago. Remove remaining pragma reference. Change-Id: I66c556863d47dc17d2ffdc6c23aa524df6aade80 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24fvp: Remove unnecessary default casedp-arm
The default case is impossible to hit as the `power_level` is already checked earlier. Avoids a clang warning. Change-Id: I707463c843adc748ee9aa1d2313f9ab7dab3a8ab Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Include missing header in arm_bl2_setup.cdp-arm
Change-Id: I4108ce8d1fe7d3fd51a5a96d43b9134c23b8399b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Merge pull request #938 from masahir0y/tools_sharedanh-arm
Collect headers shared between TF and host-tools into include/tools_share
2017-05-24mbedtls: Use `MBEDTLS_SHA256_SMALLER` in ARM platformsAntonio Nino Diaz
This options enables an implementation of SHA-256 that has a smaller code footprint (~1.6 KB less) but is also ~30% slower. For ARM platforms, code size is currently considered more important than execution speed in the mbed TLS crypto module. Added a small note about this option to the documentation of the authentication framework. Change-Id: I4c0b221ea5d3466465261316ba07b627fa01b233 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-24FVP,Juno: switch FVP and Juno to use generic TBBR OID headerMasahiro Yamada
The header tbbr_oid.h contains OIDs obtained by ARM Ltd. so there is no good reason to use platform_oid.h Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-24cert: move platform_oid.h to include/tools_share for all platformsMasahiro Yamada
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide any value (at least technically). For easier use of TBBR, this commit allows platforms to reuse the OIDs obtained by ARM Ltd. This will be useful for non-ARM vendors that do not need their own extension fields in their certificate files. The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the backward compatibility. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-22Merge pull request #939 from dp-arm/dp/AArch32_tbbrdanh-arm
Add TBBR and FWU support for AArch32
2017-05-16Merge pull request #942 from soby-mathew/sm/fix_juno_build_errdanh-arm
Juno: Fix AArch32 sp_min build
2017-05-16Juno: Fix AArch32 sp_min buildSoby Mathew
The commit abd2aba99ef108e0d0bb5d71c0b6e9c47ca26377 introduced a regression to the AArch32 sp_min Juno build. This patch fixes that. Change-Id: I4b141717684d6aee60c761ea17f23170aa6708c3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-05-16Merge pull request #935 from davidcunado-arm/dc/mbed_apidanh-arm
mbedtls: Namespace update for TF specific macros
2017-05-16Merge pull request #934 from sandrine-bailleux-arm/sb/break-headers-circular-depdanh-arm
Break circular dependency in FVP and Nvidia header files
2017-05-15AArch32: Add BL2U supportYatharth Kochar
Add support for firmware upgrade on AArch32. This patch has been tested on the FVP models. NOTE: Firmware upgrade on Juno AArch32 is not currently supported. Change-Id: I1ca8078214eaf86b46463edd14740120af930aec Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-15AArch32: Add `TRUSTED_BOARD_BOOT` supportdp-arm
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode. To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#define MBEDTLS_HAVE_UDBL` when `MBEDTLS_HAVE_INT32` is defined. This is a workaround for "https://github.com/ARMmbed/mbedtls/issues/708" NOTE: TBBR support on Juno AArch32 is not currently supported. Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-12Migrate ARM platforms to use TF_MBEDTLS_KEY_ALGDavid Cunado
A previous patch superseded the MBEDTLS_KEY_ALG. This patch updates the ARM platforms to use the new TF_MBEDTLS_KEY_ALG define. Change-Id: Ie0e1bc272e127e879ac58e7cfcbe268751d7688e Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-12FVP: Break circular dependency in platform header filesSandrine Bailleux
We used to have the following circular dependency in the FVP platform header files: +-> arm_def.h ---> platform_def.h ---> fvp_def.h --+ |__________________________________________________| This patch breaks it by not including 'arm_def.h' from 'fvp_def.h'. Change-Id: I280d906559e3343dd38764029e77c0ea768b4fec Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2017-05-11Add missing SPDX headerDavid Cunado
A new file added as part of arm-trusted-firmware#927 was missing the SPDX license identifier - this patch adds the missing identifier. Change-Id: Id1355f2bdca930b7e65bb54eff7e6c764ebb0d96 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-05-11Merge pull request #927 from jeenu-arm/state-switchdavidcunado-arm
Execution state switch
2017-05-04Introduce ARM SiP service to switch execution stateJeenu Viswambharan
In AArch64, privileged exception levels control the execution state (a.k.a. register width) of the immediate lower Exception Level; i.e. whether the lower exception level executes in AArch64 or AArch32 state. For an exception level to have its execution state changed at run time, it must request the change by raising a synchronous exception to the higher exception level. This patch implements and adds such a provision to the ARM SiP service, by which an immediate lower exception level can request to switch its execution state. The execution state is switched if the request is: - raised from non-secure world; - raised on the primary CPU, before any secondaries are brought online with CPU_ON PSCI call; - raised from an exception level immediately below EL3: EL2, if implemented; otherwise NS EL1. If successful, the SMC doesn't return to the caller, but to the entry point supplied with the call. Otherwise, the caller will observe the SMC returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built for AArch32, the feature is not supported, and the call will always fail. For the ARM SiP service: - Add SMC function IDs for both AArch32 and AArch64; - Increment the SiP service minor version to 2; - Adjust the number of supported SiP service calls. Add documentation for ARM SiP service. Fixes ARM-software/tf-issues#436 Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Add macro to check whether the CPU implements an ELJeenu Viswambharan
Replace all instances of checks with the new macro. Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-04-29Merge branch 'integration' into tf_issue_461Scott Branden
2017-04-29Move defines in utils.h to utils_def.h to fix shared header compile issuesScott Branden
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. This allows the header files to be shared between host and target builds for shared defines. Recently types.h has been included in utils.h as well as some function prototypes. Because of the inclusion of types.h conflicts exist building host tools abd these header files now. To solve this problem, move the defines to utils_def.h and have this included by utils.h and change header files to only include utils_def.h and not pick up the new types.h being introduced. Fixes ARM-software/tf-issues#461 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Remove utils_def.h from utils.h This patch removes utils_def.h from utils.h as it is not required. And also makes a minor change to ensure Juno platform compiles. Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
2017-04-24CSS: Allow system suspend only via PSCI SYSTEM_SUSPEND APISoby Mathew
The CSS power management layer previously allowed to suspend system power domain level via both PSCI CPU_SUSPEND and PSCI SYSTEM_SUSPEND APIs. System suspend via PSCI CPU_SUSPEND was always problematic to support because of issues with targeting wakeup interrupts to suspended cores before the per-cpu GIC initialization is done. This is not the case for PSCI SYSTEM_SUSPEND API because all the other cores are expected to be offlined prior to issuing system suspend and PSCI CPU_ON explicit calls will be made to power them on. Hence the Juno platform used to downgrade the PSCI CPU_SUSPEND request for system power domain level to cluster level by overriding the default `plat_psci_pm_ops` exported by CSS layer. Given the direction the new CSS platforms are evolving, it is best to limit the system suspend only via PSCI SYSTEM_SUSPEND API for all CSS platforms. This patch makes changes to allow system suspend only via PSCI SYSTEM_SUSPEND API. The override of `plat_psci_ops` for Juno is removed. Change-Id: Idb30eaad04890dd46074e9e888caeedc50a4b533 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-04-21Merge pull request #910 from dp-arm/dp/AArch32-juno-portdavidcunado-arm
Add AArch32 support for Juno
2017-04-20AArch32: Add SP_MIN support for JUNOYatharth Kochar
This patch adds support for SP_MIN on JUNO platform. The changes include addition of AArch32 assembly files, JUNO specific SP_MIN make file and miscellaneous changes in ARM platform files to enable support for SP_MIN. Change-Id: Id1303f422fc9b98b9362c757b1a4225a16fffc0b Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20Changes to support execution in AArch32 state for JUNOYatharth Kochar
Following steps are required to boot JUNO in AArch32 state: 1> BL1, in AArch64 state, loads BL2. 2> BL2, in AArch64 state, initializes DDR. Loads SP_MIN & BL33 (AArch32 executable)images. Calls RUN_IMAGE SMC to go back to BL1. 3> BL1 writes AArch32 executable opcodes, to load and branch at the entrypoint address of SP_MIN, at HI-VECTOR address and then request for warm reset in AArch32 state using RMR_EL3. This patch makes following changes to facilitate above steps: * Added assembly function to carry out step 3 above. * Added region in TZC that enables Secure access to the HI-VECTOR(0xFFFF0000) address space. * AArch32 image descriptor is used, in BL2, to load SP_MIN and BL33 AArch32 executable images. A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that controls above changes. By default this flag is disabled. NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO. Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
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