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2017-09-15imx8qm/imx8qxp: enable standby suspendAnson Huang
As suspend with last CPU power down needs SCFW support, and it is NOT ready now, in order to enable kernel suspend function earlier for modules to start debugging suspend resume function, this patch adds standby suspend for now. Will add last CPU power down suspend function when SCFW is ready. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12i.mx8mq: Add basic support for i.mx8mqBai Ping
Add basic support for i.MX8MQ. 1. SMP support is ok. 2. basic suspend/resume support is ok. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12PSCI: support killing offline CPUAnson Huang
When secondary CPUs are offline, some platforms do NOT support shutting down secondary CPUs by themself, need to use other online CPU to shutdown those CPUs which are being offline, this patch adds killing offline CPUs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-06-28Introduce TF_LDFLAGSDouglas Raillard
Use TF_LDFLAGS from the Makefiles, and still append LDFLAGS as well to the compiler's invocation. This allows passing extra options from the make command line using LDFLAGS. Document new LDFLAGS Makefile option. Change-Id: I88c5ac26ca12ac2b2d60a6f150ae027639991f27 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-28Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53danh-arm
Apply workarounds for A53 Cat A Errata 835769 and 843419
2017-06-28Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisonsdanh-arm
Resolve signed-unsigned comparison issues
2017-06-28Merge pull request #978 from etienne-lms/minor-builddanh-arm
Minor build fixes
2017-06-27Resolve signed-unsigned comparison issuesDavid Cunado
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL() macro to TF constants. This has caused some signed-unsigned comparison warnings / errors in the TF static analysis. This patch addresses these issues by migrating impacted variables from signed ints to unsigned ints and vice verse where applicable. Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-26Merge pull request #994 from soby-mathew/sm/fwu_fixdavidcunado-arm
Fix FWU and cache helper optimization
2017-06-23Merge pull request #976 from etienne-lms/minor-pscidavidcunado-arm
psci: minor fixes in lib
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-23Merge pull request #995 from davidcunado-arm/dc/init_regdavidcunado-arm
Fully initialise essential control registers
2017-06-23PSCI: use same function prototype as in header fileEtienne Carriere
Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22psci: minor fixes in libEtienne Carriere
Call svc_suspend_finish if registered. psci_get_stat() is static to psci_stat.c Fix types used in comparison. Fix coding style (empty line between variable definition and instructions block). Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22Apply workarounds for A53 Cat A Errata 835769 and 843419Douglas Raillard
These errata are only applicable to AArch64 state. See the errata notice for more details: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm048406/index.html Introduce the build options ERRATA_A53_835769 and ERRATA_A53_843419. Enable both of them for Juno. Apply the 835769 workaround as following: * Compile with -mfix-cortex-a53-835769 * Link with --fix-cortex-a53-835769 Apply the 843419 workaround as following: * Link with --fix-cortex-a53-843419 The erratum 843419 workaround can lead the linker to create new sections suffixed with "*.stub*" and 4KB aligned. The erratum 835769 can lead the linker to create new "*.stub" sections with no particular alignment. Also add support for LDFLAGS_aarch32 and LDFLAGS_aarch64 in Makefile for architecture-specific linker options. Change-Id: Iab3337e338b7a0a16b0d102404d9db98c154f8f8 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-22aarch32: Apply workaround for errata 813419 of Cortex-A57Dimitris Papastamos
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-21Fully initialise essential control registersDavid Cunado
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-21Exit early if size zero for cache helpersSoby Mathew
This patch enables cache helper functions `flush_dcache_range`, `clean_dcache_range` and `invalidate_dcache_range` to exit early if the size argument specified is zero Change-Id: I0b63e8f4bd3d47ec08bf2a0b0b9a7ff8a269a9b0 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-20Merge pull request #983 from dp-arm/dp/aarch32-erratadavidcunado-arm
aarch32: Implement errata workarounds for Cortex A53 and A57
2017-06-20aarch32: Implement errata workarounds for Cortex A57Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: I98a85fd92e32ae4259f4ec5b3e93cffc87090064 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement errata workarounds for Cortex A53Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement cpu_rev_var_hs()Dimitris Papastamos
Helper function to assist with errata workaround application. Change-Id: Idba42ca238442cc826f43444dbfa754e433a5e5e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20xlat_tables_v2: fix signed/unsigned comparisonsVarun Wadekar
This patch changes input param level in xlat_tables_print_internal() to an unsigned int to fix the signed/unsigned comparison warnings. The compiler complains about these warnings, thus halting the build flow for Tegra platforms. Change-Id: Ieccc262a63daca7a26ca6a14d81466397af8b89f Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Tegra: enable 'signed-comparison' compilation warning/errorsVarun Wadekar
This patch enables the 'sign-compare' flag, to enable warning/errors for comparisons between signed/unsigned variables. The warning has been enabled for all the Tegra platforms, to start with. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-01Add support for Cortex-A75 and Cortex-A55 CPUsDavid Wang
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-24compiler-rt: Remove unused int_util.[ch] filesdp-arm
Change-Id: I32fc523e3178b7e50191682241904d52499ff708 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Use a callee-saved register to be AAPCS-compliantdp-arm
x8 is not a callee-saved register and can be corrupted. Use x19 instead to be AAPCS-compliant. Fixes ARM-software/tf-issues#478 Change-Id: Ib4f114c36f4c11351ae856f953c45dca92b27c3b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-22Merge pull request #945 from antonio-nino-diaz-arm/an/xlat-dependencydanh-arm
xlat: Fix missing header file dependency
2017-05-22Merge pull request #939 from dp-arm/dp/AArch32_tbbrdanh-arm
Add TBBR and FWU support for AArch32
2017-05-18xlat: Fix missing header file dependencyAntonio Nino Diaz
xlat_tables_arch.h uses the platform macro `PLAT_VIRT_ADDR_SPACE_SIZE`. This macro is defined in xlat_tables_private.h only if the platform still uses the deprecated `ADDR_SPACE_SIZE`. Change-Id: I1c3b12ebd96bdfe9bf94b26d440c03bc0f8c0b24 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-16Simplify assert() to reduce memory usageAntonio Nino Diaz
The behaviour of assert() now depends on the value of the new optional platform define `PLAT_LOG_LEVEL_ASSERT`. This defaults to `LOG_LEVEL` if not defined by the platform. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_VERBOSE`, it prints the file name, line and asserted expression. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_INFO`, it prints the file name and line. - If not, it doesn't print anything. Note the old behaviour was to print the function name whereas now it prints the file name. This reduces memory usage because the file name is shared between all assert calls in a given file. Also, the default behaviour in debug builds is to no longer print the asserted expression, greatly reducing the string usage. For FVP debug builds this change saves approximately: No TBBR TBBR BL1 1.6 KB 2.2 KB BL2 1.7 KB 2.1 KB BL31 2.6 KB 3.3 KB Change-Id: I2947569d593df0b25611dc3c7a6096f42155c115 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-12Merge pull request #930 from antonio-nino-diaz-arm/an/fixes-xlat-v2davidcunado-arm
Minor fixes to the xlat tables lib v2
2017-05-12Hook up LLVM compiler-rt in the build systemdp-arm
This patch enables compiler-rt for the AArch32 target. The code is not used for AArch64 as the architecture supports the 64-bit division and modulo operations natively. Change-Id: I1703a92872b0bb56ac0b98c67193830683963b13 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-12Import builtins from LLVM compiler-rt projectdp-arm
These are needed to provide division and modulo operations for the AArch32 target. This code is entirely unmodified. Imported from compiler-rt master branch as of May 4 2017. Change-Id: I001e1809f2afd4bf8d4cc3d2296798809f607144 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-11Merge pull request #927 from jeenu-arm/state-switchdavidcunado-arm
Execution state switch
2017-05-09Minor fixes to the xlat tables lib v2Antonio Nino Diaz
- Fix some comments. - Remove duplicated definition. - Make xlat_arch_get_max_supported_pa() private in aarch64. Change-Id: I629237209cfb2ce7b0c4bd539d63dd81d45b2edd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-05Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bitdavidcunado-arm
Fix execute-never permissions in xlat tables libs
2017-05-04Merge pull request #925 from dp-arm/dp/spdxdavidcunado-arm
Use SPDX license identifiers
2017-05-04Introduce ARM SiP service to switch execution stateJeenu Viswambharan
In AArch64, privileged exception levels control the execution state (a.k.a. register width) of the immediate lower Exception Level; i.e. whether the lower exception level executes in AArch64 or AArch32 state. For an exception level to have its execution state changed at run time, it must request the change by raising a synchronous exception to the higher exception level. This patch implements and adds such a provision to the ARM SiP service, by which an immediate lower exception level can request to switch its execution state. The execution state is switched if the request is: - raised from non-secure world; - raised on the primary CPU, before any secondaries are brought online with CPU_ON PSCI call; - raised from an exception level immediately below EL3: EL2, if implemented; otherwise NS EL1. If successful, the SMC doesn't return to the caller, but to the entry point supplied with the call. Otherwise, the caller will observe the SMC returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built for AArch32, the feature is not supported, and the call will always fail. For the ARM SiP service: - Add SMC function IDs for both AArch32 and AArch64; - Increment the SiP service minor version to 2; - Adjust the number of supported SiP service calls. Add documentation for ARM SiP service. Fixes ARM-software/tf-issues#436 Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Add macro to check whether the CPU implements an ELJeenu Viswambharan
Replace all instances of checks with the new macro. Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-02Fix execute-never permissions in xlat tables libsAntonio Nino Diaz
Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-02Merge pull request #923 from nmenon/fix_xlat_1davidcunado-arm
xlat lib: Don't set mmap_attr_t enum to be -1
2017-05-02xlat lib: Don't set mmap_attr_t enum to be -1Nishanth Menon
-1 is not a defined mmap_attr_t type. Instead of using invalid enum types, we can either choose to define a INVALID type OR handle the condition specifically. Since the usage of mmap_region_attr is limited, it is easier to just handle the error condition specifically and return 0 or -1 depending on success or fail. Fixes: ARM-Software/tf-issues#473 Fixes: 28fa2e9ee8f4 ("xlat lib: Use mmap_attr_t type consistently") Signed-off-by: Nishanth Menon <nm@ti.com>
2017-04-29Merge branch 'integration' into tf_issue_461Scott Branden
2017-04-29Move defines in utils.h to utils_def.h to fix shared header compile issuesScott Branden
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. This allows the header files to be shared between host and target builds for shared defines. Recently types.h has been included in utils.h as well as some function prototypes. Because of the inclusion of types.h conflicts exist building host tools abd these header files now. To solve this problem, move the defines to utils_def.h and have this included by utils.h and change header files to only include utils_def.h and not pick up the new types.h being introduced. Fixes ARM-software/tf-issues#461 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Remove utils_def.h from utils.h This patch removes utils_def.h from utils.h as it is not required. And also makes a minor change to ensure Juno platform compiles. Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
2017-04-24Merge pull request #909 from sandrine-bailleux-arm/sb/xlat-lib-misc-improvementsdavidcunado-arm
xlat lib: Use mmap_attr_t type consistently
2017-04-21Merge pull request #910 from dp-arm/dp/AArch32-juno-portdavidcunado-arm
Add AArch32 support for Juno
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