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2020-03-07Enable CPU, FP, L2 retention counters to 64 cyclesNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2019-12-13plat: imx: Enable L2 ECC & parity for A72 clusterAnson Huang
As per design team's suggestion, L2 cache's ECC & parity should be enabled for A72 cluster. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-12-13imx: add system_reset2 support for i.MX8QM/i.MX8QXAnson Huang
Add system_reset2 support for i.MX8QM/i.MX8QX to support WARM/COLD/BOARD reset. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2019-10-11Replace deprecated __ASSEMBLY__ macro with __ASSEMBLER__Balint Dobszay
Change-Id: I497072575231730a216220f84a6d349a48eaf5e3 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-10-08delay: correct timeout_init_us()Yann Gautier
The function has to use read_cntpct_el0() to update the counter, and not read_cntfrq_el0(). Change-Id: I9c676466e784c3122e9ffc2d87e66708797086e7 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-07Merge "Explicitly disable the SPME bit in MDCR_EL3" into integrationSoby Mathew
2019-10-07Merge "Neoverse N1 Errata Workaround 1542419" into integrationSoby Mathew
2019-10-07Explicitly disable the SPME bit in MDCR_EL3Petre-Ionut Tudor
Currently the MDCR_EL3 initialisation implicitly disables MDCR_EL3.SPME by using mov_imm. This patch makes the SPME bit more visible by explicitly disabling it and documenting its use in different versions of the architecture. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: I221fdf314f01622f46ac5aa43388f59fa17a29b3
2019-10-04Neoverse N1 Errata Workaround 1542419laurenw-arm
Coherent I-cache is causing a prefetch violation where when the core executes an instruction that has recently been modified, the core might fetch a stale instruction which violates the ordering of instruction fetches. The workaround includes an instruction sequence to implementation defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap handler to execute a TLB inner-shareable invalidation to an arbitrary address followed by a DSB. Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com> Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6
2019-10-03delay: timeout detection supportLionel Debieve
Introduce timeout_init_us/timeout_elapsed() delay tracking with CNTPCT. timeout_init_us(some_timeout_us); returns a reference to detect timeout for the provided microsecond delay value from current time. timeout_elapsed(reference) return true/false whether the reference timeout is elapsed. Cherry picked from OP-TEE implementation [1]. [1] commit 33d30a74502b ("core: timeout detection support") Minor: - Remove stm32mp platform duplicated implementation. - Add new include in marvell ble.mk Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org> Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iaef6d43c11a2e6992fb48efdc674a0552755ad9c
2019-10-03Introducing support for Cortex-A65AEImre Kis
Change-Id: I1ea2bf088f1e001cdbd377cbfb7c6a2866af0422 Signed-off-by: Imre Kis <imre.kis@arm.com>
2019-10-03Merge changes from topic "stm32mp_corrections_w40" into integrationSoby Mathew
* changes: gpio: stm32_gpio: do not mix error code types fdts: stm32mp1: move FDCAN to PLL4_R mmc: increase delay between ACMD41 retries crypto: stm32_hash: align stm32_hash_update() prototype
2019-10-03Merge "Add missing support for BL2_AT_EL3 in XIP memory" into integrationSoby Mathew
2019-10-03crypto: stm32_hash: align stm32_hash_update() prototypeYann Gautier
Use size_t for length parameter in header file, as in .c file. Change-Id: I310f2a6159cde1c069b4f814f6558c2488c203ec Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-10-02Introducing support for Cortex-A65Imre Kis
Change-Id: I645442d52a295706948e2cac88c36c1a3cb0bc47 Signed-off-by: Imre Kis <imre.kis@arm.com>
2019-10-02Add missing support for BL2_AT_EL3 in XIP memoryLionel Debieve
Add the missing flag for aarch32 XIP memory mode. It was previously added in aarch64 only. Minor: Correct the aarch64 missing flag. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: Iac0a7581a1fd580aececa75f97deb894858f776f
2019-10-01Merge "Cortex_hercules: Add support for Hercules-AE" into integrationSoby Mathew
2019-09-30Cortex_hercules: Add support for Hercules-AEArtsem Artsemenka
Not tested on FVP Model. Change-Id: Iedebc5c1fbc7ea577e94142b7feafa5546f1f4f9 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
2019-09-27Merge "AArch32: Disable Secure Cycle Counter" into integrationSoby Mathew
2019-09-27Merge changes from topic "ld/stm32-authentication" into integrationSoby Mathew
* changes: stm32mp1: add authentication support for stm32image bsec: move bsec_mode_is_closed_device() service to platform crypto: stm32_hash: Add HASH driver
2019-09-27Merge changes from topic "mp/giv3-discovery" into integrationSoby Mathew
* changes: Migrate ARM platforms to use the new GICv3 API Adding new optional PSCI hook pwr_domain_on_finish_late GICv3: Enable multi socket GIC redistributor frame discovery
2019-09-26AArch32: Disable Secure Cycle CounterAlexei Fedorov
This patch changes implementation for disabling Secure Cycle Counter. For ARMv8.5 the counter gets disabled by setting SDCR.SCCD bit on CPU cold/warm boot. For the earlier architectures PMCR register is saved/restored on secure world entry/exit from/to Non-secure state, and cycle counting gets disabled by setting PMCR.DP bit. In 'include\aarch32\arch.h' header file new ARMv8.5-PMU related definitions were added. Change-Id: Ia8845db2ebe8de940d66dff479225a5b879316f8 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-09-26Merge changes I0283fc2e,Ib476d024,Iada05f7c into integrationPaul Beesley
* changes: hikey: fix to load FIP by partition table. hikey960: fix to load FIP by partition table drivers: partition: support different block size
2019-09-25Migrate ARM platforms to use the new GICv3 APIMadhukar Pappireddy
This patch invokes the new function gicv3_rdistif_probe() in the ARM platform specific gicv3 driver. Since this API modifies the shared GIC related data structure, it must be invoked coherently by using the platform specific pwr_domain_on_finish_late hook. Change-Id: I6efb17d5da61545a1c5a6641b8f58472b31e62a8 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-09-25Adding new optional PSCI hook pwr_domain_on_finish_lateMadhukar Pappireddy
This PSCI hook is similar to pwr_domain_on_finish but is guaranteed to be invoked with the respective core and cluster are participating in coherency. This will be necessary to safely invoke the new GICv3 API which modifies shared GIC data structures concurrently. Change-Id: I8e54f05c9d4ef5712184c9c18ba45ac97a29eb7a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-09-25GICv3: Enable multi socket GIC redistributor frame discoveryMadhukar Pappireddy
This patch provides declaration and definition of new GICv3 driver API: gicv3_rdistif_probe().This function delegates the responsibility of discovering the corresponding Redistributor base frame to each CPU itself. It is a modified version of gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform unlike the previous approach in which only the Primary CPU did the discovery of all the Redistributor frames for every CPU. The flush operations as part of gicv3_driver_init() function are made necessary even for platforms with WARMBOOT_ENABLE_DCACHE_EARLY because the GICv3 driver data structure contents are accessed by CPU with D-Cache turned off during power down operations. Change-Id: I1833e81d3974b32a3e4a3df4766a33d070982268 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-09-20bsec: move bsec_mode_is_closed_device() service to platformLionel Debieve
This BSEC service is a platform specific service. Implementation moved to the platform part. Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I1f70ed48a446860498ed111acce01187568538c9
2019-09-20crypto: stm32_hash: Add HASH driverLionel Debieve
The driver manages the HASH processor IP on STM32MP1 Signed-off-by: Lionel Debieve <lionel.debieve@st.com> Change-Id: I3b67c80c16d819f86b951dae29a6c465e51ad585
2019-09-18drivers: partition: support different block sizeHaojian Zhuang
The block size of some storage device is 4096-byte long, such as UFS. But PARTITION_BLOCK_SIZE is defined as 512-byte long. So replace it by PLAT_PARTITION_BLOCK_SIZE. Make it configurable in platform. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Change-Id: Iada05f7c646d0a0f2c0d3b8545540b3cb7153de3
2019-09-16Merge changes from topic "raspberry-pi-4-support" into integrationSandrine Bailleux
* changes: Add fdt_add_reserved_memory() helper function qemu: Move and generalise FDT PSCI fixup
2019-09-16Merge changes from topic "raspberry-pi-4-support" into integrationSandrine Bailleux
* changes: rpi3: Move rng driver to drivers rpi3: Move VC mailbox driver into generic drivers directory rpi3: Move rpi3_hw.h header file to include/rpi_hw.h
2019-09-13Add fdt_add_reserved_memory() helper functionAndre Przywara
If a firmware component like TF-A reserves special memory regions for its own or secure payload services, it should announce the location and size of those regions to the non-secure world. This will avoid disappointment when some rich OS tries to acccess this memory, which will likely end in a crash. The traditional way of advertising reserved memory using device tree is using the special memreserve feature of the device tree blob (DTB). However by definition those regions mentioned there do not prevent the rich OS to map this memory, which may lead to speculative accesses to this memory and hence spurious bus errors. A safer way of carving out memory is to use the /reserved-memory node as part of the normal DT structure. Besides being easier to setup, this also defines an explicit "no-map" property to signify the secure-only nature of certain memory regions, which avoids the rich OS to accidentally step on it. Add a helper function to allow platform ports to easily add a region. Change-Id: I2b92676cf48fd3bdacda05b5c6b1c7952ebed68c Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-09-13rpi3: Move rng driver to driversAndre Przywara
To allow sharing the driver between the RPi3 and RPi4, move the random number generator driver into the generic driver directory. Change-Id: Iae94d7cb22c6bce3af9bff709d76d4caf87b14d1 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-09-13qemu: Move and generalise FDT PSCI fixupAndre Przywara
The QEMU platform port scans its device tree to advertise PSCI as the CPU enable method. It does this by scanning *every* node in the DT and check whether its compatible string starts with "arm,cortex-a". Then it sets the enable-method to PSCI, if it doesn't already have one. Other platforms might want to use this functionality as well, so let's move it out of the QEMU platform directory and make it more robust by fixing some shortcomings: - A compatible string starting with a certain prefix is not a good way to find the CPU nodes. For instance a "arm,cortex-a72-pmu" node will match as well and is in turn favoured with an enable-method. - If the DT already has an enable-method, we won't change this to PSCI. Those two issues will for instance fail on the Raspberry Pi 4 DT. To fix those problems, we adjust the scanning method: The DT spec says that all CPU nodes are subnodes of the mandatory /cpus node, which is a subnode of the root node. Also each CPU node has to have a device_type = "cpu" property. So we find the /cpus node, then scan for a subnode with the proper device_type, forcing the enable-method to "psci". We have to restart this search after a property has been patched, as the node offsets might have changed meanwhile. This allows this routine to be reused for the Raspberry Pi 4 later. Change-Id: I00cae16cc923d9f8bb96a9b2a2933b9a79b06139 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-09-13rpi3: Move VC mailbox driver into generic drivers directoryAndre Przywara
To allow sharing the driver between the RPi3 and RPi4, move the mailbox driver into the generic driver directory. Change-Id: I463e49acf82b02bf004f3d56482b7791f3020bc0 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-09-13Merge "Refactor ARMv8.3 Pointer Authentication support code" into integrationSoby Mathew
2019-09-13Refactor ARMv8.3 Pointer Authentication support codeAlexei Fedorov
This patch provides the following features and makes modifications listed below: - Individual APIAKey key generation for each CPU. - New key generation on every BL31 warm boot and TSP CPU On event. - Per-CPU storage of APIAKey added in percpu_data[] of cpu_data structure. - `plat_init_apiakey()` function replaced with `plat_init_apkey()` which returns 128-bit value and uses Generic timer physical counter value to increase the randomness of the generated key. The new function can be used for generation of all ARMv8.3-PAuth keys - ARMv8.3-PAuth specific code placed in `lib\extensions\pauth`. - New `pauth_init_enable_el1()` and `pauth_init_enable_el3()` functions generate, program and enable APIAKey_EL1 for EL1 and EL3 respectively; pauth_disable_el1()` and `pauth_disable_el3()` functions disable PAuth for EL1 and EL3 respectively; `pauth_load_bl31_apiakey()` loads saved per-CPU APIAKey_EL1 from cpu-data structure. - Combined `save_gp_pauth_registers()` function replaces calls to `save_gp_registers()` and `pauth_context_save()`; `restore_gp_pauth_registers()` replaces `pauth_context_restore()` and `restore_gp_registers()` calls. - `restore_gp_registers_eret()` function removed with corresponding code placed in `el3_exit()`. - Fixed the issue when `pauth_t pauth_ctx` structure allocated space for 12 uint64_t PAuth registers instead of 10 by removal of macro CTX_PACGAKEY_END from `include/lib/el3_runtime/aarch64/context.h` and assigning its value to CTX_PAUTH_REGS_END. - Use of MODE_SP_ELX and MODE_SP_EL0 macro definitions in `msr spsel` instruction instead of hard-coded values. - Changes in documentation related to ARMv8.3-PAuth and ARMv8.5-BTI. Change-Id: Id18b81cc46f52a783a7e6a09b9f149b6ce803211 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
2019-09-13Merge changes from topic "jc/rsa-pkcs" into integrationSoby Mathew
* changes: Remove RSA PKCS#1 v1.5 support from cert_tool Add documentation for new KEY_SIZE option Add cert_create tool support for RSA key sizes Support larger RSA key sizes when using MBEDTLS
2019-09-13Merge changes I08cf22df,I535ee414,Ie84cfc96,I8c35ce4e,If7649764, ... into ↵Soby Mathew
integration * changes: mediatek: mt8183: Support coreboot configuration mediatek: mt8183: support system reset mediatek: mt8183: pass platform parameters mediatek: mt8183: add GPIO driver mediatek: mt8183: support system off mediatek: mt8183: support CPU hotplug mediatek: mt8183: refine GIC driver
2019-09-12Support larger RSA key sizes when using MBEDTLSJustin Chadwell
Previously, TF-A could not support large RSA key sizes as the configuration options passed to MBEDTLS prevented storing and performing calculations with the larger, higher-precision numbers required. With these changes to the arguments passed to MBEDTLS, TF-A now supports using 3072 (3K) and 4096 (4K) keys in certificates. Change-Id: Ib73a6773145d2faa25c28d04f9a42e86f2fd555f Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-12Invalidate dcache build option for bl2 entry at EL3Hadi Asyrafi
Some of the platform (ie. Agilex) make use of CCU IPs which will only be initialized during bl2_el3_early_platform_setup. Any operation to the cache beforehand will crash the platform. Hence, this will provide an option to skip the data cache invalidation upon bl2 entry at EL3 Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I2c924ed0589a72d0034714c31be8fe57237d1f06
2019-09-12Merge "libc: fix sparse warning for __assert()" into integrationSoby Mathew
2019-09-12Merge changes from topic "jc/mte_enable" into integrationSoby Mathew
* changes: Add documentation for CTX_INCLUDE_MTE_REGS Enable MTE support in both secure and non-secure worlds
2019-09-12Merge "Add UBSAN support and handlers" into integrationSoby Mathew
2019-09-12Merge changes from topic "amlogic-refactoring" into integrationSoby Mathew
* changes: amlogic: Fix includes order amlogic: Fix header guards amlogic: Fix prefixes in the SoC specific files amlogic: Fix prefixes in the PM code amlogic: Fix prefixes in the SCPI related code amlogic: Fix prefixes in the MHU code amlogic: Fix prefixes in the SIP/SVC code amlogic: Fix prefixes in the thermal driver amlogic: Fix prefixes in the private header file amlogic: Fix prefixes in the efuse driver amlogic: Fix prefixes in the platform macros file amlogic: Fix prefixes in the helpers file amlogic: Rework Makefiles amlogic: Move the SIP SVC code to common directory amlogic: Move topology file to common directory amlogic: Move thermal code to common directory amlogic: Move MHU code to common directory amlogic: Move efuse code to common directory amlogic: Move platform macros assembly file to common directory amlogic: Introduce unified private header file amlogic: Move SCPI code to common directory amlogic: Move the SHA256 DMA driver to common directory amlogic: Move assembly helpers to common directory amlogic: Introduce directory parameters in the makefiles meson: Rename platform directory to amlogic
2019-09-11Merge "mbedtls: use #include <...> instead of "..."" into integrationSoby Mathew
2019-09-11Add UBSAN support and handlersJustin Chadwell
This patch adds support for the Undefined Behaviour sanitizer. There are two types of support offered - minimalistic trapping support which essentially immediately crashes on undefined behaviour and full support with full debug messages. The full support relies on ubsan.c which has been adapted from code used by OPTEE. Change-Id: I417c810f4fc43dcb56db6a6a555bfd0b38440727 Signed-off-by: Justin Chadwell <justin.chadwell@arm.com>
2019-09-11libc: fix sparse warning for __assert()Masahiro Yamada
Sparse warns this: lib/libc/assert.c:29:6: error: symbol '__assert' redeclared with different type (originally declared at include/lib/libc/assert.h:36) - different modifiers Add __dead2 to match the header declaration and C definition. I also changed '__dead2 void' to 'void __dead2' for the consistency with other parts. Change-Id: Iefa4f0e787c24fa7e7e499d2e7baf54d4deb49ef Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2019-09-10mediatek: mt8183: pass platform parameterskenny liang
Add plat parameter structs to support BL2 to pass variable-length, variable-type parameters to BL31. The parameters are structured as a link list. During BL31 setup time, we traverse the list to process each parameter. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: Ie84cfc9606656fb1d2780a68cadf27e09afa6628
2019-09-10mediatek: mt8183: support CPU hotplugkenny liang
- Add DCM driver - Add SPMC driver - Implement core and cluster power on/off handlers Change-Id: I902002f8ea6f98fd73bf259188162b10d3939c72 Signed-off-by: kenny liang <kenny.liang@mediatek.com>
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