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2017-07-12drivers: add tzc380 supportPeng Fan
Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12Enable CPU, FP, L2 retention counters to 64 cyclesNitin Garg
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2017-07-12Add interface for enabling wake up from WFI in EL3Anson Huang
Add interface to enable FIQ routing in SCR_EL3 to make interrupts can wake up ARM from WFI when executing in EL3, as all interrupts are signaled as FIQ in EL3. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add necessary type definitionsAnson Huang
Add bool/true/false type to make it easy for porting code from other platforms. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-06-28ARM plat changes to enable CryptoCell integrationSoby Mathew
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Add headers to enable CryptoCell integrationSoby Mathew
This patch adds header files with required declarations and macro definitions to enable integration with CryptoCell SBROM version `CC712 – Release 1.0.0.1061`. These headers enable ARM Trusted Firmware to build and link with CryptoCell SBROM library. Change-Id: I501eda7fe1429acb61db8e1cab78cc9aee9c1871 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Merge pull request #978 from etienne-lms/minor-builddanh-arm
Minor build fixes
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-23Merge pull request #995 from davidcunado-arm/dc/init_regdavidcunado-arm
Fully initialise essential control registers
2017-06-23context_mgmt: declare extern cm_set_next_context() for AArch32Etienne Carriere
This change avoids warning when setting -Wmissing-prototypes to compile bl1_context_mgmt.c. Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23bl: security_state should be of type unsigned intEtienne Carriere
security_state is either 0 or 1. Prevent sign conversion potential error (setting -Werror=sign-conversion results in a build error). Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22aarch32: Apply workaround for errata 813419 of Cortex-A57Dimitris Papastamos
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-21Fully initialise essential control registersDavid Cunado
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-20aarch32: Fix L2CTRL definition for Cortex A57 and A72Dimitris Papastamos
Fixes ARM-software/tf-issues#495 Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement errata workarounds for Cortex A53Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20sp_min: Implement `sp_min_plat_runtime_setup()`Dimitris Papastamos
On ARM platforms before exiting from SP_MIN ensure that the default console is switched to the runtime serial port. Change-Id: I0ca0d42cc47e345d56179eac16aa3d6712767c9b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-14include: add U()/ULL() macros for constantsVarun Wadekar
This patch uses the U() and ULL() macros for constants, to fix some of the signed-ness defects flagged by the MISRA scanner. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Add U() macro to share constants between C and other sourcesVarun Wadekar
This patch adds the U(_x) macros to utils_def.h to allow constants to be shared between C and other sources. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-09Fix stdlib defines for AArch32Soby Mathew
Some of the macro defines in the header files of `include/lib/stdlib/machine/` folder are not correct for AArch32. This patch fixes the same. Change-Id: I8bfaf638a7986fd902648d2074537bd26c313cb3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-07stdlib: support AARCH32 in endian head fileHaojian Zhuang
Add the support of AARCH32 in endian head file. The code is also imported from FreeBSD 11.0. It's based on commit in below. commit 4e3a5b429989b4ff621682ff1462f801237bd551 Author: mmel <mmel@FreeBSD.org> Date: Tue Nov 10 12:02:41 2015 +0000 ARM: Remove trailing whitespace from sys/arm/include No functional changes. Approved by: kib (mentor) Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-07stdlib: import endian head file from freebsdHaojian Zhuang
Import endian head files from FreeBSD 11.0. The link of FreeBSD source code is https://github.com/freebsd/freebsd Import machine/endian.h from sys/arm64/include/endian.h in FreeBSD. commit d09ff72cef8e35dbf62f7363dcbf07b453f06243 Author: andrew <andrew@FreeBSD.org> Date: Mon Mar 23 11:54:56 2015 +0000 Add the start of the arm64 machine headers. This is the subset needed to start getting userland libraries building. Reviewed by: imp Sponsored by: The FreeBSD Foundation Import sys/endian.h from sys/sys/endian.h in FreeBSD. commit 3c3fa2f5b0c7640373fcbcc3f667bf7794e8e609 Author: phk <phk@FreeBSD.org> Date: Thu May 20 06:16:13 2010 +0000 Fix some way-past-brucification complaints from FlexeLint. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-05Merge pull request #964 from soby-mathew/sm/rsapss_supdanh-arm
Add support for RSASSAPSS algorithm
2017-06-05Merge pull request #963 from soby-mathew/sm/scmi_devdanh-arm
Add SCMI power domain and system power protocol support
2017-06-05Merge pull request #960 from jeenu-arm/cpu-libsdanh-arm
Add support for Cortex-A75 and Cortex-A55 CPUs
2017-06-05Merge pull request #962 from antonio-nino-diaz-arm/an/fwu-checksdanh-arm
FWU: Check for overlaps when loading images, introduce `FWU_SMC_IMAGE_RESET`
2017-06-05Add SCMI support for Juno platformSoby Mathew
This patch adds the memory map region for the SCMI payload memory and maps the Juno core indices to SCMI power domains via the `plat_css_core_pos_to_scmi_dmn_id_map` array. Change-Id: I0d2bb2a719ff5b6a9d8e22e91e1625ab14453665 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-05CSS: Add SCMI driver for SCPSoby Mathew
This patch adds the SCMI driver for communicating with SCP. The power domain management and system power management protocol of the SCMI specification[1] is implemented in the driver. The SCP power management abstraction layer for SCMI for CSS power management is also added. A new buid option `CSS_USE_SCMI_DRIVER` is introduced to select SCMI driver over SCPI. [1] ARM System Control and Management Interface v1.0 (SCMI) Document number: ARM DEN 0056A Change-Id: I67265615a17e679a2afe810b9b0043711ba09dbb Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-05Add support for RSASSAPSS algorithm in mbedtls crypto driverSoby Mathew
This patch adds support for RSASSA-PSS Signature Algorithm for X509 certificates in mbedtls crypto driver. Now the driver supports RSA PKCS2_1 standard as mandated by TBBR. NOTE: With this patch, the PKCS1_5 standard compliant RSA signature is deprecated. Change-Id: I9cf6d073370b710cc36a7b374a55ec96c0496461 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-01FWU: Introduce FWU_SMC_IMAGE_RESETAntonio Nino Diaz
This SMC is as a means for the image loading state machine to go from COPYING, COPIED or AUTHENTICATED states to RESET state. Previously, this was only done when the authentication of an image failed or when the execution of the image finished. Documentation updated. Change-Id: Ida6d4c65017f83ae5e27465ec36f54499c6534d9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-06-01Add support for Cortex-A75 and Cortex-A55 CPUsDavid Wang
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-31Merge pull request #955 from hzhuang1/ufsdanh-arm
Add ufs stack and designware phy
2017-05-31drivers: add designware ufs driverHaojian Zhuang
Initialized the designware UFS PHY. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-05-31drivers: add ufs stackHaojian Zhuang
If UFS device is initialized, we could just make it out of hibernation by UFS_FLAGS_SKIPINIT. And vendor's dirver is always focus on PHY setting. We could use UFS driver directly if it exits from hibernation. There're eight LUNs in UFS device. The UFS driver only provides the read/write API with LUN. User could define his own read/write since user may want to access different LUNs. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-05-30Merge pull request #949 from antonio-nino-diaz-arm/an/printf-memorydavidcunado-arm
Reduce code size when building with Trusted Board Boot enabled
2017-05-24Cortex-A53: add some bit definitionsHaojian Zhuang
Add some bit definitions of CPUACTLR register in Cortex-A53 CPU library. Change-Id: I142fd8ac4b06dd651a32e22951e71cdebbea123a Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
2017-05-24build: Introduce clang supportdp-arm
Only the compiler is switched to clang. The assembler and linker are provided by the GCC toolchain. clang is used to build TF when the base name of the path assigned to `CC` contains the string 'clang'. `CROSS_COMPILE` is still needed and should point to the appropriate GCC toolchain. Tested with clang 3.9.x and 4.0.x. Change-Id: I53236d64e3c83ad27fc843bae5fcdae30f2e325e Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Merge pull request #938 from masahir0y/tools_sharedanh-arm
Collect headers shared between TF and host-tools into include/tools_share
2017-05-24mbedtls: Use `tf_snprintf` instead of `snprintf`Antonio Nino Diaz
The Trusted Firmware uses a subset of the APIs provided by mbed TLS. This subset internally uses `snprintf`, but the only format specifier used is '%d', which is supported by `tf_snprintf`. This patch makes mbed TLS use `tf_snprintf` instead of `snprintf`, saving 3 KB in both debug and release builds when TBBR is enabled. Change-Id: I7f992a21015930d7c0f4660e7a28ceefd60b9597 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-24Introduce `tf_snprintf`Antonio Nino Diaz
This is a reduced version of `snprintf` that only supports formats '%d', '%i' and '%u'. It can be used when the full `snprintf` is not needed in order to save memory. If it finds an unknown format specifier, it prints an error message and panics. Change-Id: I2cb06fcdf74cda2c43caf73ae0762a91499fc04e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-24cert: move platform_oid.h to include/tools_share for all platformsMasahiro Yamada
Platforms aligned with TBBR are supposed to use their own OIDs, but defining the same macros with different OIDs does not provide any value (at least technically). For easier use of TBBR, this commit allows platforms to reuse the OIDs obtained by ARM Ltd. This will be useful for non-ARM vendors that do not need their own extension fields in their certificate files. The OIDs of ARM Ltd. have been moved to include/tools_share/tbbr_oid.h Platforms can include <tbbr_oid.h> instead of <platform_oid.h> by defining USE_TBBR_DEFS as 1. USE_TBBR_DEFS is 0 by default to keep the backward compatibility. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-23fip: move headers shared between TF and fiptool to include/tools_shareMasahiro Yamada
Some header files need to be shared between TF and host programs. For fiptool, two headers are copied to the tools/fiptool directory, but it looks clumsy. This commit introduces a new directory, include/tools_share, which collects headers that should be shared between TF and host programs. This will clarify the interface exposed to host tools. We should add new headers to this directory only when we really need to do so. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-22Merge pull request #939 from dp-arm/dp/AArch32_tbbrdanh-arm
Add TBBR and FWU support for AArch32
2017-05-19Merge pull request #936 from antonio-nino-diaz-arm/an/assert-memdavidcunado-arm
Simplify assert() to reduce memory usage
2017-05-16Merge pull request #935 from davidcunado-arm/dc/mbed_apidanh-arm
mbedtls: Namespace update for TF specific macros
2017-05-16Simplify assert() to reduce memory usageAntonio Nino Diaz
The behaviour of assert() now depends on the value of the new optional platform define `PLAT_LOG_LEVEL_ASSERT`. This defaults to `LOG_LEVEL` if not defined by the platform. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_VERBOSE`, it prints the file name, line and asserted expression. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_INFO`, it prints the file name and line. - If not, it doesn't print anything. Note the old behaviour was to print the function name whereas now it prints the file name. This reduces memory usage because the file name is shared between all assert calls in a given file. Also, the default behaviour in debug builds is to no longer print the asserted expression, greatly reducing the string usage. For FVP debug builds this change saves approximately: No TBBR TBBR BL1 1.6 KB 2.2 KB BL2 1.7 KB 2.1 KB BL31 2.6 KB 3.3 KB Change-Id: I2947569d593df0b25611dc3c7a6096f42155c115 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-15AArch32: Add BL2U supportYatharth Kochar
Add support for firmware upgrade on AArch32. This patch has been tested on the FVP models. NOTE: Firmware upgrade on Juno AArch32 is not currently supported. Change-Id: I1ca8078214eaf86b46463edd14740120af930aec Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-15AArch32: Add `TRUSTED_BOARD_BOOT` supportdp-arm
This patch adds `TRUSTED_BOARD_BOOT` support for AArch32 mode. To build this patch the "mbedtls/include/mbedtls/bignum.h" needs to be modified to remove `#define MBEDTLS_HAVE_UDBL` when `MBEDTLS_HAVE_INT32` is defined. This is a workaround for "https://github.com/ARMmbed/mbedtls/issues/708" NOTE: TBBR support on Juno AArch32 is not currently supported. Change-Id: I86d80e30b9139adc4d9663f112801ece42deafcf Signed-off-by: dp-arm <dimitris.papastamos@arm.com> Co-Authored-By: Yatharth Kochar <yatharth.kochar@arm.com>
2017-05-12Merge pull request #930 from antonio-nino-diaz-arm/an/fixes-xlat-v2davidcunado-arm
Minor fixes to the xlat tables lib v2
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