summaryrefslogtreecommitdiff
path: root/docs
AgeCommit message (Collapse)Author
2019-09-05meson: Rename platform directory to amlogicCarlo Caione
Meson is the internal code name for the SoC family. The correct name for the platform should be Amlogic. Change the name of the platform directory. Signed-off-by: Carlo Caione <ccaione@baylibre.com> Change-Id: Icc140e1ea137f12117acbf64c7dcb1a8b66b345d
2019-09-04doc: Updated user guide with new Mbed TLS version numberzelalem-aweke
Signed-off-by: zelalem-aweke <zelalem.aweke@arm.com> Change-Id: Ib12ecc0b283274c74cdfa57caf9e1a105dce3afe
2019-08-29Added SPCI to the glossaryArtsem Artsemenka
Change-Id: I576ae161477f4a69336d15a7741e566bb103124a Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com>
2019-08-01doc: Suggest to use the latest version 8.3 of GCCLouis Mayencourt
At the time of writting, GCC 8.3-2019.03 is the latest version available on developer.arm.com. Switch to bare-metal toolchain (arm-eabi-) for AArch32. This allows to have a finer control on the use of floating-point and SIMD instructions. Change-Id: I4438401405eae1e5f6d531b0162e8fa06f69135e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-07-25Merge "Romlib makefile refactoring and script rewriting" into integrationSoby Mathew
2019-07-24Merge "rockchip: px30: support px30" into integrationSoby Mathew
2019-07-22Romlib makefile refactoring and script rewritingImre Kis
The features of the previously existing gentbl, genvar and genwrappers scripts were reimplemented in the romlib_generator.py Python script. This resulted in more readable and maintainable code and the script introduces additional features that help dependency handling in makefiles. The assembly templates were separated from the script logic and were collected in the 'templates' directory. The targets and their dependencies were reorganized in the makefile and the dependency handling of included index files is possible now. Incremental build is available in case of modifying the index files. Signed-off-by: Imre Kis <imre.kis@arm.com> Change-Id: I79f65fab9dc5c70d1f6fc8f57b2a3009bf842dc5
2019-07-19Merge "intel: Adds support for Agilex platform" into integrationSoby Mathew
2019-07-18doc: Complete the storage abstraction layer docLouis Mayencourt
Add uml sequence and class diagram to illustrate the behavior of the storage abstraction layer. Change-Id: I338262729f8034cc3d3eea1d0ce19cca973a91bb Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
2019-07-17intel: Adds support for Agilex platformHadi Asyrafi
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib2ad2068abdf0b204c5cb021ea919581adaca4ef
2019-07-12doc: Generate PlantUML diagrams automaticallyPaul Beesley
Currently we have some pre-rendered versions of certain diagrams in SVG format. These diagrams have corresponding PlantUML source that can be rendered automatically as part of the documentation build, removing the need for any intermediate files. This patch adds the Sphinx "plantuml" extension, replaces references to the pre-rendered SVG files within the documents, and finally removes the SVG files and helper script. New requirements for building the docs are the "sphinxcontrib-plantuml" Python module (added to the pip requirements.txt file) and the Graphviz package (provides the "dot" binary) which is in the Ubuntu package repositories. Change-Id: I24b52ee40ff79676212ed7cff350294945f1b50d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-07-12Merge "Remove references to old project name from common files" into integrationSandrine Bailleux
2019-07-12Merge "Fix RST rendering problem" into integrationSandrine Bailleux
2019-07-10Rename Cortex-Deimos to Cortex-A77Balint Dobszay
Change-Id: I755e4c42242d9a052570fd1132ca3d937acadb13 Signed-off-by: Balint Dobszay <balint.dobszay@arm.com>
2019-07-10Remove references to old project name from common filesJohn Tsichritzis
The project has been renamed from "Arm Trusted Firmware (ATF)" to "Trusted Firmware-A (TF-A)" long ago. A few references to the old project name that still remained in various places have now been removed. This change doesn't affect any platform files. Any "ATF" references inside platform files, still remain. Change-Id: Id97895faa5b1845e851d4d50f5750de7a55bf99e Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-09Fix RST rendering problemJohn Tsichritzis
Change-Id: Ic5aab23b549d0bf8e0f7053b46fd59243214aac1 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-09rockchip: px30: support px30XiaoDong Huang
px30 is a Quad-core soc and Cortex-a53 inside. This patch supports the following functions: 1. basic platform setup 2. power up/off cpus 3. suspend/resume cpus 4. suspend/resume system 5. reset system 6. power off system Change-Id: I73d55aa978096c078242be921abe0ddca9e8f67e Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
2019-07-08docs: removing references to GitHubJohn Tsichritzis
Change-Id: Ibdee91ad337ee362872924d93e82f5b5e47e63d9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-07-04Merge changes from topic "lw/n1_errata_fixes" into integrationSandrine Bailleux
* changes: Removing redundant ISB instructions Workaround for Neoverse N1 erratum 1275112 Workaround for Neoverse N1 erratum 1262888 Workaround for Neoverse N1 erratum 1262606 Workaround for Neoverse N1 erratum 1257314 Workaround for Neoverse N1 erratum 1220197 Workaround for Neoverse N1 erratum 1207823 Workaround for Neoverse N1 erratum 1165347 Workaround for Neoverse N1 erratum 1130799 Workaround for Neoverse N1 erratum 1073348
2019-07-02Workaround for Neoverse N1 erratum 1275112lauwal01
Neoverse N1 erratum 1275112 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: If7fe55fe92e656fa6aea12327ab297f2e6119833 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262888lauwal01
Neoverse N1 erratum 1262888 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUECTLR_EL1 system register, which disables the MMU hardware prefetcher. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ib733d748e32a7ea6a2783f3d5a9c5e13eee01105 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1262606lauwal01
Neoverse N1 erratum 1262606 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which delays instruction fetch after branch misprediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Idd980e9d5310232d38f0ce272862e1fb0f02ce9a Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1257314lauwal01
Neoverse N1 erratum 1257314 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR3_EL1 system register, which prevents parallel execution of divide and square root instructions. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I54f0f40ff9043efee40d51e796b92ed85b394cbb Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1220197lauwal01
Neoverse N1 erratum 1220197 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUECTLR_EL1 system register, which disables write streaming to the L2. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I9c3373f1b6d67d21ee71b2b80aec5e96826818e8 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1207823lauwal01
Neoverse N1 erratum 1207823 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: Ia932337821f1ef0d644db3612480462a8d924d21 Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1165347lauwal01
Neoverse N1 erratum 1165347 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set two bits in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I163d0ea00578245c1323d2340314cdc3088c450d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1130799lauwal01
Neoverse N1 erratum 1130799 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I252bc45f9733443ba0503fefe62f50fdea61da6d Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-02Workaround for Neoverse N1 erratum 1073348lauwal01
Neoverse N1 erratum 1073348 is a Cat B erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR_EL1 system register, which disables static prediction. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdoc-466751330-10325/index.html Change-Id: I674126c0af6e068eecb379a190bcf7c75dcbca8e Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
2019-07-01Merge changes from topic "banned_api_list" into integrationSoby Mathew
* changes: Fix the License header template in imx_aipstz.c docs: Add the list of banned/use with caution APIs
2019-07-01docs: Add the list of banned/use with caution APIsSoby Mathew
Credit to sam.ellis@arm.com for the input to create the list. Change-Id: Id70a8eddc5f2490811bebb278482c61950f10cce Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2019-06-25Merge "doc: Fix typo in file interrupt-framework-design.rst" into integrationJohn Tsichritzis
2019-06-24Fix links in documentationJohn Tsichritzis
Change-Id: Ifef4d634b4a34d23f42f61df5e326a1cc05d3844 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-06-22doc: Fix typo in file interrupt-framework-design.rstPeng Donglin
Signed-off-by: Peng Donglin <dolinux.peng@gmail.com> Change-Id: I459e7d056735222f6f34e275dbdaf9a389d193fc
2019-06-20Merge "doc: Isolate security-related build options" into integrationJohn Tsichritzis
2019-06-17stm32mp1: update doc for U-Boot compilationYann Gautier
U-Boot should be compiled with stm32mp15_trusted_defconfig which is supported since tag v2019.07-rc1 with commit [1]. The creation of the U-Boot binary with stm32 header is done at U-Boot compilation step, it is no more required to call the extra command. [1] https://git.denx.de/?p=u-boot.git;a=commit;h=015289580f81 Change-Id: Ia875c22184785fc2e02ad07993a649069cd5ce34 Signed-off-by: Yann Gautier <yann.gautier@st.com>
2019-06-12doc: Isolate security-related build optionsAmbroise Vincent
Reference security specific build options from the user guide. Change-Id: I0e1efbf47d914cf3c473104175c702ff1a80eb67 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-11Merge "Update maintainers list" into integrationSoby Mathew
2019-06-10Update maintainers listJohn Tsichritzis
Also sort alphabetically the links at the bottom, a couple of them were not sorted. Change-Id: I49a1dbe9e56a36c5fdbace8e4c8b9a5270bc2984 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-06-10Merge "doc: Document E and W build options" into integrationSoby Mathew
2019-06-06Neoverse N1: Introduce workaround for Neoverse N1 erratum 1315703Andre Przywara
Neoverse N1 erratum 1315703 is a Cat A (rare) erratum [1], present in older revisions of the Neoverse N1 processor core. The workaround is to set a bit in the implementation defined CPUACTLR2_EL1 system register, which will disable the load-bypass-store feature. [1] http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.pjdocpjdoc-466751330-1032/index.html Change-Id: I5c708dbe0efa4daa0bcb6bd9622c5efe19c03af9 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2019-06-06doc: Document E and W build optionsAmbroise Vincent
Change-Id: I0d9dbef7041fcf950bcafcdbbc17c72b4dea9e40 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-06-03Merge "doc: Enable automatic labels for page titles" into integrationJohn Tsichritzis
2019-06-03Add information about the mailing list in the docsJohn Tsichritzis
Change-Id: I41ce5323c33a81db13c5cc40de1ac4e221a10cd8 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-31Removing IRC related info from the documentationJohn Tsichritzis
Change-Id: I5cf8c70a304bf5869cbeb12fa8d39171cff48ebd Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-30doc: Enable automatic labels for page titlesPaul Beesley
Automatic labelling of document titles is a prerequisite for converting the format of cross-document links. Sphinx will generate (via the enabled extension) a hidden link target for each document title and this can be referred to later, from another page, to link to the target. The plugin options being used require Sphinx >= 2.0.0 so a requirements.txt file has been added. This file is used with the pip package manager for Python so that the correct dependencies are installed. Change-Id: Ic2049db5804aa4a6447608ba4299de958ce0a87d Signed-off-by: Paul Beesley <paul.beesley@arm.com>
2019-05-30Further fixes to documentation linksJohn Tsichritzis
Change-Id: Ib021c721652d96f6c06ea18741f19a72bba1d00f Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-29Merge "Cortex-A55: workarounds for errata 1221012" into integrationPaul Beesley
2019-05-28Cortex-A55: workarounds for errata 1221012Ambroise Vincent
The workaround is added to the Cortex-A55 cpu specific file. The workaround is disabled by default and have to be explicitly enabled by the platform integrator. Change-Id: I3e6fd10df6444122a8ee7d08058946ff1cc912f8 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
2019-05-28Fix documentation linksJohn Tsichritzis
Change-Id: Ic09e74f22b43fba51ee17cd02b5e1dc5d8e0bb63 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
2019-05-24Merge "Add support for Branch Target Identification" into integrationPaul Beesley
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-24 05:37:58 +0000