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2018-06-21Merge pull request #1392 from dp-arm/dp/cve_2018_3639Dimitris Papastamos
Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75 Conflicts: services/arm_arch_svc/arm_arch_svc_setup.c
2018-03-20Update user guideJoel Hutton
Following Out of Box testing for v1.5 release: Update host OS version to Ubuntu 16.04 Clarify configuration files needed for checkpatch Add note on using Linaro precompiled binaries Change-Id: Ia4ae61e01128ddff1a288972ddf84b79370fa52c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
2018-03-15Update model support in User GuideDavid Cunado
The CI has been updated to run tests against the AEMv8-A RevC model, FVP_Base_RevC-2xAEMv8A, which is available from the Fast Model releases on Connected Community [1]. Additionally, the CI now also includes the Cortex-A55x4, Cortex-A75x4 and Cortex-A55x4-A75x4 Base models. [1] https://developer.arm.com/products/system-design/fixed-virtual-platforms Change-Id: I57806f3b2a8121211490a7aa0089dcae566d8635 Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-15Update change-log.rst for v1.5David Cunado
Updated change-log.rst with summary of changes since release v1.4. Change-Id: I56b5a30d13a5a7099942535cbaeff0e2a5c5804e Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-15Update Arm TF references to TF-ADan Handley
Update Arm Trusted Firmware references in the upstream documents to Trusted Firmware-A (TF-A). This is for consistency with and disambiguation from Trusted Firmware-M (TF-M). Also update other Arm trademarks, e.g. ARM->Arm, ARMv8->Armv8-A. Change-Id: I8bb0e18af29c6744eeea2dc6c08f2c10b20ede22 Signed-off-by: Dan Handley <dan.handley@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
2018-03-13Docs: Update design guide for dynamic configSoby Mathew
This patch updates the `firmware-design.rst` document for changes in ARM-TF for supporting dynamic configuration features as presented in `Secure Firmware BoF SFO'17`[1]. The patch also updates the user-guide for 2 build options for FVP pertaining to dynamic config. [1] https://www.slideshare.net/linaroorg/bof-device-tree-and-secure-firmware-bof-sfo17310 Change-Id: Ic099cf41e7f1a98718c39854e6286d884011d445 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-03-08Merge pull request #1277 from hzhuang1/testing/bl2_el3_v0.6davidcunado-arm
hikey: migrate to BL2_EL3
2018-03-07Merge pull request #1239 from arve-android/trusty-fixesdavidcunado-arm
Trusty fixes
2018-03-05trusty: Add boot parameter documentationArve Hjønnevåg
Change-Id: Ibfb75145e3a31ae2106eedfbe4a91c2e31bb9f2a
2018-03-05hikey960: migrate to bl2_el3Haojian Zhuang
Since non-TF ROM is used in HiKey960 platform (Hisilicon Hi3660 SoC), replace BL1 by BL2_EL3 in normal boot mode. When flush images in recovery mode, keep to use BL1. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-03-05hikey: migrate to bl2_el3Haojian Zhuang
Since non-TF ROM is used in HiKey platform (Hisilicon Hi6220 SoC), replace BL1 by BL2_EL3 in normal boot mode. When we recovery images in recovery mode, keep to use BL1. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2018-02-28FVP: Allow building for DynamIQ systemsJeenu Viswambharan
FVPs that model DynamIQ configuration implements all CPUs in a single cluster. I.e., such models have a single cluster with more than 4 CPUs. This differs from existing default build configuration for FVP where up to 4 CPUs are assumed per cluster. To allow building for DynamIQ configuration, promote the macro FVP_MAX_CPUS_PER_CLUSTER as a build option to have it set from the build command line. The value of the build option defaults to 4. Change-Id: Idc3853bc95f680869b434b011c2dbd733e40c6ce Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-02-28Merge pull request #1287 from davidcunado-arm/dc/fix_misradavidcunado-arm
Update ULL() macro and instances of ull to comply with MISRA
2018-02-27Merge pull request #1283 from jeenu-arm/sdei-fixesdavidcunado-arm
SDEI fixes
2018-02-27Update ULL() macro and instances of ull to comply with MISRADavid Cunado
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
2018-02-27SDEI: Add prioritisation clarificationJeenu Viswambharan
To make exception handling amongst Secure components, require that SDEI exception priorities must be assigned the lowest among Secure priorities. Clarify documentation to this effect. Change-Id: I92524b7b7e9b3fa06a10c86372bc3c4dd18c00ad Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-02-26BL1: Deprecate the `bl1_init_bl2_mem_layout()` APISoby Mathew
The `bl1_init_bl2_mem_layout()` API is now deprecated. The default weak implementation of `bl1_plat_handle_post_image_load()` calculates the BL2 memory layout and populates the same in x1(r1). This ensures compatibility for the deprecated API. Change-Id: Id44bdc1f572dc42ee6ceef4036b3a46803689315 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-26Add image_id to bl1_plat_handle_post/pre_image_load()Soby Mathew
This patch adds an argument to bl1_plat_post/pre_image_load() APIs to make it more future proof. The default implementation of these are moved to `plat_bl1_common.c` file. These APIs are now invoked appropriately in the FWU code path prior to or post image loading by BL1 and are not restricted to LOAD_IMAGE_V2. The patch also reorganizes some common platform files. The previous `plat_bl2_el3_common.c` and `platform_helpers_default.c` files are merged into a new `plat_bl_common.c` file. NOTE: The addition of an argument to the above mentioned platform APIs is not expected to have a great impact because these APIs were only recently added and are unlikely to be used. Change-Id: I0519caaee0f774dd33638ff63a2e597ea178c453 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2018-02-23Fix Foundation FVP instructions in User GuideAntonio Nino Diaz
The Arm Trusted Firmware is built by default for ARMv8-A version 8.0. However, the Foundation FVP runs by default in the highest version of the architecture it supports. This causes problems when trying to run the Arm Trusted Firmware on it. This patch adds a note to the User Guide about this problem. Change-Id: I0220fe1a9c66c2292149ad4a7ffe5e27ba08ab28 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2018-02-12Merge pull request #1256 from jeenu-arm/tsp-ehfdavidcunado-arm
TSP changes for EHF
2018-02-06interrupt-framework-design.rst: Cosmetic changesJeenu Viswambharan
Change-Id: Id2e2800af59ca35fc0c4cfdddd9f5c5afd56a4db Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-02-06TSPD: Require NS preemption along with EL3 exception handlingJeenu Viswambharan
At present, the build option TSP_NS_INTR_ASYNC_PREEMPT controls how Non-secure interrupt affects TSPs execution. When TSP is executing: 1. When TSP_NS_INTR_ASYNC_PREEMPT=0, Non-secure interrupts are received at the TSP's exception vector, and TSP voluntarily preempts itself. 2. When TSP_NS_INTR_ASYNC_PREEMPT=1, Non-secure interrupts causes a trap to EL3, which preempts TSP execution. When EL3 exception handling is in place (i.e., EL3_EXCEPTION_HANDLING=1), FIQs are always trapped to EL3. On a system with GICv3, pending NS interrupts while TSP is executing will be signalled as FIQ (which traps to EL3). This situation necessitates the same treatment applied to case (2) above. Therefore, when EL3 exception handling is in place, additionally require that TSP_NS_INTR_ASYNC_PREEMPT is set to one 1. Strictly speaking, this is not required on a system with GICv2, but the same model is uniformly followed regardless, for simplicity. Relevant documentation updated. Change-Id: I928a8ed081fb0ac96e8b1dfe9375c98384da1ccd Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-02-06Deprecate one EL3 interrupt routing model with EL3 exception handlingJeenu Viswambharan
When ARM Trusted Firmware is built with EL3_EXCEPTION_HANDLING=1, EL3 interrupts (INTR_TYPE_EL3) will always preempt both Non-secure and secure execution. The interrupt management framework currently treats EL3 interrupt routing as valid. For the above reason, this patch makes them invalid when EL3_EXCEPTION_HANDLING is in effect. Change-Id: I95bca8f5dc8df8eb0ff6f305cfba098611522a39 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2018-02-02bl1: add bl1_plat_handle_{pre,post}_image_load()Masahiro Yamada
Just like bl2_, add pre/post image load handlers for BL1. No argument is needed since BL2 is the only image loaded by BL1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-02-02bl2: add bl2_plat_handle_pre_image_load()Masahiro Yamada
There are cases where we need to manipulate image information before the load. For example, for decompressing data, we cannot load the compressed images to their final destination. Instead, we need to load them to the temporary buffer for the decompressor. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-29Merge pull request #1246 from sandrine-bailleux-arm/topics/sb/fix-cnp-docdavidcunado-arm
Fix documentation for CnP bit
2018-01-29Fix documentation for CnP bitSandrine Bailleux
The CnP bit documentation in the Firmware Design Guide incorrectly used the term "Page Entries" instead of "Processing Elements". Fix that. Change-Id: Ie44ee99c281b7b1a9ad90fba2c7d109f12425507 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
2018-01-29docs: hikey: Fix typoAndreas Färber
The correct name of the manufacturer is LeMaker. Signed-off-by: Andreas Färber <afaerber@suse.de>
2018-01-25Merge pull request #1232 from masahir0y/uniphierdavidcunado-arm
uniphier: migrate to BL2-AT-EL3
2018-01-24Merge pull request #1193 from jwerner-chromium/JW_corebootdavidcunado-arm
New console API and coreboot support [v4]
2018-01-24uniphier: switch to BL2-AT-EL3 and remove BL1 supportMasahiro Yamada
UniPhier platform implements non-TF boot ROM. Prior to the BL2-AT-EL3 support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2 is entered at EL1-S. Now, this platform is able to avoid this waste. Enable the BL2_AT_EL3 option, and remove BL1. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2018-01-19Add default crash console code to hook up to new console APIJulius Werner
This patch expands the weak stubs for the plat_crash_console_xxx functions in common platform code to use the new console API for crash output. This should make crash console output "just work" for most cases without the need for the platform to explicitly set up a crash console. For cases where the normal console framework doesn't work (e.g. very early crashes, before the platform can register any consoles), platforms are still able to override the functions just like before. This feature requires the MULTI_CONSOLE_API compile-time flag to work. For builds which don't have it set, this patch has no practical effect. Change-Id: I80dd161cb43f9db59a0bad2dae33c6560cfac584 Signed-off-by: Julius Werner <jwerner@chromium.org>
2018-01-19Merge pull request #1200 from robertovargas-arm/bl2-el3davidcunado-arm
Add BL2_AT_EL3 build option
2018-01-18bl2-el3: Add documentation for BL2 at EL3Roberto Vargas
Update firmware-design.rst, porting-guide.rst and user-guide.rst with the information about BL2 at EL3. Firmware-design.rst is also update to explain how to test this feauture with FVP. Change-Id: I86d64bc64594e13eb041cea9cefa3f7f3fa745bd Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-15Merge pull request #1217 from robertovargas-arm/doc-plat_try_next_boot_sourcedavidcunado-arm
Add documentation about plat_try_next_boot_source to bl1_platform_setup
2018-01-12Merge pull request #1197 from dp-arm/dp/amudavidcunado-arm
AMUv1 support
2018-01-11AMU: Add plat interface to select which group 1 counters to enableDimitris Papastamos
A new platform macro `PLAT_AMU_GROUP1_COUNTERS_MASK` controls which group 1 counters should be enabled. The maximum number of group 1 counters supported by AMUv1 is 16 so the mask can be at most 0xffff. If the platform does not define this mask, no group 1 counters are enabled. A related platform macro `PLAT_AMU_GROUP1_NR_COUNTERS` is used by generic code to allocate an array to save and restore the counters on CPU suspend. Change-Id: I6d135badf4846292de931a43bb563077f42bb47b Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-11Workaround for CVE-2017-5715 on Cortex A57 and A72Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Change-Id: I97788d38463a5840a410e3cea85ed297a1678265 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2018-01-10Add documentation about plat_try_next_boot_source to bl1_platform_setupRoberto Vargas
If boot redundancy is required in BL1 then the initialization of the boot sequence must be done in bl1_platform_setup. In BL2, we had to add a new function, bl2_preload_setup, because bl2_platform_setup is called after the images are loaded, making it invalid for the boot sequence initialization. Change-Id: I5c177ff142608ed38b4192288b06614343b2b83b Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2018-01-03Merge pull request #1204 from davidcunado-arm/rv/fip_tooldavidcunado-arm
Add padding at the end of the last entry
2018-01-03Merge pull request #1206 from davidcunado-arm/dc/update_userguidedavidcunado-arm
Update dependencies for ARM TF
2018-01-03docs: Update the ToC end marker description in the documentJett Zhou
Change-Id: I2e29a63f08aed3b8ea0bb10170a3d55b8d033e62 Signed-off-by: Jett Zhou <jett.zhou@arm.com> Signed-off-by: David Cunado <david.cunado@arm.com>
2017-12-24Merge pull request #1203 from masahir0y/uniphierdavidcunado-arm
uniphier: a bundle of fixes
2017-12-21Update dependencies for ARM TFDavid Cunado
ARM TF has been tested as part of its CI system with the following dependencies updated: - Linaro binaries: 17.04 --> 17.10 - mbed TLS library: 2.4.2 --> 2.6.0 The version of AEM, Cortex-A and Foundation models that ARM TF is tested on has also been updated: - v11.1 build 11.1:22 --> v11.2 build 11.2:33 - v8.9 build 0.8:8805 --> v9.0 build 0.8:9005 This patch updates the user guide documentation to reflect these changes to the dependencies. Additionally, links to Linaro resources have been updated. Change-Id: I9ea5cb76e7443c9dbb0c9525069f450a02f59e58 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-12-20doc: uniphier: reformat reStructuredText manuallyMasahiro Yamada
Commit 6f6257476754 ("Convert documentation to reStructuredText") automatically converted all documents by a tool. I see some parts were converted in an ugly way (or, at least, it is not my intention). Also, the footnote is apparently broken. I checked this document by my eyes, and reformated it so that it looks nicer both in plain text and reST form. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-12-15Add Secure Partition Manager (SPM) design documentAntonio Nino Diaz
This patch adds documentation that describes the design of the Secure Partition Manager and the specific choices in their current implementation. The document "SPM User Guide" has been integrated into the design document. Change-Id: I0a4f21a2af631c8aa6c739d97a5b634f3cb39991 Co-authored-by: Achin Gupta <achin.gupta@arm.com> Co-authored-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-12-11Merge pull request #1178 from davidcunado-arm/dc/enable_svedavidcunado-arm
Enable SVE for Non-secure world
2017-12-09Merge pull request #1186 from antonio-nino-diaz-arm/an/poplar-docdavidcunado-arm
poplar: Fix format of documentation
2017-12-06poplar: Fix format of documentationAntonio Nino Diaz
The document was being rendered incorrectly. Change-Id: I6e243d17d7cb6247f91698bc195eb0f6efeb7d17 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-12-05Merge pull request #1157 from antonio-nino-diaz-arm/an/rpi3davidcunado-arm
Introduce AArch64 Raspberry Pi 3 port
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