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2017-06-29Remove Markdown documentationDouglas Raillard
Removed Markdown documents as they have been converted to reStructuredText. Change-Id: I3148222eb31258f158f64de4ddcdda4b232ce483 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-29Convert documentation to reStructuredTextDouglas Raillard
Due to recent issues in the rendering of the documentation on GitHub and some long-standing issues like the lack of automatic table of content in Markdown, the documentation has been converted to reStructuredText. Basic constructs looks pretty similar to Markdown. Automatically convert GitHub markdown documentation to reStructuredText using pandoc. Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-29Fix various small issues in the documentationDouglas Raillard
Change some hard-to-convert constructs to cleaner ones. Fix a broken link. Change-Id: Ida70aa1da0af7a107b0e05eb20b8d46669a0380b Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-13uniphier: add TSP supportMasahiro Yamada
Add TSP to test BL32 without relying on external projects. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-13uniphier: support Socionext UniPhier platformMasahiro Yamada
Initial commit for Socionext UniPhier SoC support. BL1, Bl2, and BL31 are supported. Refer to docs/plat/socionext-uniphier.md for more detais. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-06-08hikey960: add documentHaojian Zhuang
Add document on HiKey960 platform and how to build. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-05-24hikey: add hikey supportHaojian Zhuang
Add the description on hikey and how to build. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-02-28Tegra: enable ECC/Parity protection for Cortex-A57 CPUsVarun Wadekar
This patch enables L2 ECC and Parity Protection for ARM Cortex-A57 CPUs for Tegra SoCs. Change-Id: I038fcd529991d0201a4951ce2730ab71b1c980f9 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-22Tegra: init normal/crash console for platformsVarun Wadekar
The BL2 fills in the UART controller ID to be used as the normal as well as the crash console on Tegra platforms. The controller ID to UART controller base address mapping is handled by each Tegra SoC the base addresses might change across Tegra chips. This patch adds the handler to parse the platform params to get the UART ID for the per-soc handlers. Change-Id: I4d167b20a59aaf52a31e2a8edf94d8d6f89598fa Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-22Tegra: add tzdram_base to plat_params_from_bl2 structVarun Wadekar
This patch adds another member, tzdram_base, to the plat_params_from_bl2 struct in order to store the TZDRAM carveout base address used to load the Trusted OS. The monitor programs the memory controller with the TZDRAM base and size in order to deny any accesses from the NS world. Change-Id: If39b8674d548175d7ccb6525c18d196ae8a8506c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-02-06zynqmp: remove RESET_TO_BL31=1 from build instructionMasahiro Yamada
RESET_TO_BL31=1 is specified by plat/xilinx/zynqmp/platform.mk with "override" directive. So, RESET_TO_BL31=1 is guaranteed without any operation on users' side. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2016-07-04Merge pull request #651 from Xilinx/zynqmp_uartdanh-arm
zynqmp: Make UART selectable
2016-06-15zynqmp: Add option to select between Cadence UARTsSoren Brinkmann
Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd UART available in the SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-06-15Merge pull request #650 from Xilinx/zynqmp-updatesdanh-arm
Zynqmp updates
2016-06-09Add support for QEMU virt ARMv8-A targetJens Wiklander
This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
2016-04-25zynqmp: FSBL->ATF handoverMichal Simek
Parse the parameter structure the FSBL populates, to populate the bl32 and bl33 image structures. Cc: Sarat Chand Savitala <saratcha@xilinx.com> Cc: petalinux-dev@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> [ SB - pass pointers to structs instead of structs - handle execution state parameter - populate bl32 SPSR - add documentation - query bootmode and consider missing handoff parameters an error when not in JTAG boot mode ] Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2016-04-25zynqmp: Revise memory configuration optionsSoren Brinkmann
Drop the current configuration options for selecting the location of the ATF and TSP (ZYNQMP_ATF_LOCATION, ZYNQMP_TSP_RAM_LOCATION). The new configuration provides one default setup (ATF in OCM, BL32 in DRAM). Additionally, the new configuration options - ZYNQMP_ATF_MEM_BASE - ZYNQMP_ATF_MEM_SIZE - ZYNQMP_BL32_MEM_BASE - ZYNQMP_BL32_MEM_SIZE can be used to freely configure the memory locations used for ATF and secure payload. Also, allow setting the BL33 entry point via PRELOADED_BL33_BASE. Cc: petalinux-dev@xilinx.com Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com>
2016-04-06Add support for Xilinx Zynq UltraScale+ MPSOCSoren Brinkmann
The Xilinx Zynq UltraScale+ MPSOC containes a quad A53 cluster. This patch adds the platform port for that SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
2015-08-01docs: fix the command to compile BL31 on TegraVarun Wadekar
This patch fixes the command line used to compile BL31 on Tegra platforms. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-07-31Tegra132: set TZDRAM_BASE to 0xF5C00000Varun Wadekar
The TZDRAM base on the reference platform has been bumped up due to some BL2 memory cleanup. Platforms can also use a different TZDRAM base by setting TZDRAM_BASE=<value> in the build command line. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-07-24tlkd: delete 'NEED_BL32' build variableVarun Wadekar
Remove the 'NEED_BL32' flag from the makefile. TLK compiles using a completely different build system and is present on the device as a binary blob. The NEED_BL32 flag does not influence the TLK load/boot sequence at all. Moreover, it expects that TLK binary be present on the host before we can compile BL31 support for Tegra. This patch removes the flag from the makefile and thus decouples both the build systems. Tested by booting TLK without the NEED_BL32 flag. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-07-24Tegra: Support for Tegra's T132 platformsVarun Wadekar
This patch implements support for T132 (Denver CPU) based Tegra platforms. The following features have been added: * SiP calls to switch T132 CPU's AARCH mode * Complete PSCI support, including 'System Suspend' * Platform specific MMIO settings * Locking of CPU vector registers Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-07-06Implement get_sys_suspend_power_state() handler for TegraVarun Wadekar
This patch implements the get_sys_suspend_power_state() handler required by the PSCI SYSTEM_SUSPEND API. The intent of this handler is to return the appropriate State-ID field which can be utilized in `affinst_suspend()` to suspend to system affinity level. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-06-11Boot Trusted OS' on Tegra SoCsVarun Wadekar
This patch adds support to run a Trusted OS during boot time. The previous stage bootloader passes the entry point information in the 'bl32_ep_info' structure, which is passed over to the SPD. The build system expects the dispatcher to be passed as an input parameter using the 'SPD=<dispatcher>' option. The Tegra docs have also been updated with this information. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2015-05-29Support for NVIDIA's Tegra T210 SoCsVarun Wadekar
T210 is the latest chip in the Tegra family of SoCs from NVIDIA. It is an ARM v8 dual-cluster (A57/A53) SoC, with any one of the clusters being active at a given point in time. This patch adds support to boot the Trusted Firmware on T210 SoCs. The patch also adds support to boot secondary CPUs, enter/exit core power states for all CPUs in the slow/fast clusters. The support to switch between clusters is still not available in this patch and would be available later. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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