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2022-05-17imx8m/hab.c: work around gcc 12.1 false positivestoradex_imx_5.4.70_2.3.0Max Krummenacher
| plat/imx/imx8m/hab.c: In function 'imx_hab_handler': | plat/imx/imx8m/hab.c:64:57: error: array subscript 0 is outside array bounds of 'uint32_t[0]' {aka 'unsigned int[]'} [-Werror=array-bounds] | 64 | #define HAB_RVT_CHECK_TARGET_ARM64 ((unsigned long)*(uint32_t *)(HAB_RVT_BASE + 0x18)) | | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2022-05-17Merge remote-tracking branch 'nxp/imx_5.4.70_2.3.0' into HEADMax Krummenacher
This merges in tag rel_imx_5.4.70_2.3.6. (rel_imx_5.4.70_2.3.7 didn't add any new commits to imx-atf.) Related-to: ELB-4410 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2022-02-11LF-5427 plat:imx8 Fix missed SCU wakeup interruptsRanjani Vaidyanathan
Handle corner cases of early of wakeup interrupts. Monitor the status of OS MU interrupt in the IRQSTR as the last step in the suspend process. If an MU interrupt is pending, switch the wakeup source to be irqsteer so that the core can woken up by the SCFW after wfi is executed. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> (cherry picked from commit c3acc399cfd8db878d6078456092ca3f63fd070b)
2021-05-03Merge remote-tracking branch 'nxp/imx_5.4.70_2.3.0' into ↵Max Krummenacher
toradex_imx_5.4.70_2.3.0 Updates to 5.4.70_2.3.2 Related-to: ELB-3957 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-03-26MLK-25358 plat: imx8m: Correct the csu sa & hpctrl settingJacky Bai
Correct the csu sa & hpctrl setting. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 9e09b4970ebce21d7a085afffbadf8851a7fd647)
2021-03-26MLK-25345 plat: imx8m: Add ddr4 dvfs sw workaround for ERR050712Jacky Bai
APB Write data corruption following MRCTRL0.mr_wr=1 while hardware-driven MR access is occurring When performing a software driven MR access, the following sequence must be done automatically before performing other APB register accesses: 1. Set MRCTRL0.mr_wr=1 2. Check for MRSTAT.mr_wr_busy=0. If not, go to step (2) 3. Check for MRSTAT.mr_wr_busy=0 again (for the second time). If not, go to step (2) Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 1eb7ad6c5ea2c47952ab5e083df9802e27c165f5)
2021-03-26MLK-25321 plat: imx8m: Add 4000mts frequency config on imx8mJacky Bai
Add the PLL frequency config for 4000mts. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> (cherry picked from commit 3409e57d59ee897e519d87d20ada926638f6be4d)
2021-03-26MLK-25293 iMX8MQ: Add version for B2Ye Li
iMX8MQ B2 chip uses same OCOTP magic value with B1. So read the ROM version to distinguish it with B1. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com> (cherry picked from commit dcfce7731ed19c6235f9b1ad3a68fbfe33b69f9a)
2021-01-12plat: imx8mp: provide uart base as build optionIgor Opaniuk
Some boards (f.e. Verdin i.MX8M Plus) use different UART base address for serial debug output, so make this value configurable (as a build option). Related-to: ELB-3208 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52 (cherry picked from commit 60a23af2e57931161169c2981bf19af3847c533c) (cherry picked from commit bbfc87c96dec60dda19438b7d6ecd2a5f4431380)
2021-01-12gitlab-ci: inital addMax Krummenacher
Build bl31 for imx8mm/imx8qm/imx8qx Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-11Revert "Add NXP's SoCs partition reboot support."Max Krummenacher
This reverts commit 13a5c7ece5a13c636e52f22b45f592b72b6453d1. With commit 13a5c7ece5a1 the SCFW will execute a reboot of the AP partition as a reaction to a psci_system_reboot, e.g. because of a Linux reboot. This does only reset the SoC partly, i.e. only IP which will not affect other partitions. As a result on Apalis iMX8 USB HSIC comes up in a state were it does not recognize our USB3503 hub correctly. Refer to the SCFW doc file sc_fw_port.pdf for more info on the various sc_reboot*, sc_reset* functionalities. Upstream-Status: Inappropriate [configuration] Related-to: ELB-2702 Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com>
2021-01-11plat: imx8mm: provide uart base as build optionIgor Opaniuk
Some boards (f.e. Verdin i.MX8M Mini) use different UART base address for serial debug output, so make this value configurable (as a build option). Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I988492ccecbc3f64a5153b381c4a97b8a0181f52 (cherry picked from commit 60a23af2e57931161169c2981bf19af3847c533c)
2020-12-01MLK-24163 plat: imx8m: Change the ddr4 dvfs debug log levelJacky Bai
This is log is just for debug purpose only. Change the ddr4 dvfs debug log print level to disable this log print by default. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2020-10-28MLK-24928 plat: imx8mp increase ISP NoC priorityJian Li
Need to increase ISP NoC priority to 0x7 (same as LCDIF panic priority) to avoid overflow in DDR4 EVK board Signed-off-by: Jian Li <jian.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-10-28MLK-24923-02 plat: imx8m: Put dram into retention when dsp lpa buffer in ocramJacky Bai
when the DSP LPA buffer is in OCRAM, dram can be put into retention to save power. This support is missed when removing the i.MX8MP A0 support, so add it back. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-10-28MLK-24923-01: Define the IRQ_IMR_NUM for each soc of imx8m separatelyJacky Bai
As the the number of IRQ IMR register on some i.MX8M SoC is different, define this macro in each SoC's dedicated header file. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-10-28MLK-24920 plat: imx8m: Fix the dram retention random hang on some imx8mq Rev2.0Jacky Bai
It seems the DRAM APB clock root slice can NOT work normally if the PLLs is power down in DSM mode. So update this clock slice's setting explictly to make it work. This piece of code is there for a long while on previous release, so just add it back to align with previous flow. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-10-23MLK-24913: plat: imx8mp: change the bl31 physical load addressJacky Bai
on i.MX8MP A1 silicon, the OCRAM space is extended to 512K + 64K, currently, OCRAM @0x960000-0x980000 is reserved for BL31, it will leave the last 64KB in non-continuous space. To provide a continuous 384KB + 64KB space for generic use, so Move the BL31 space to 0x970000-0x990000 range. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-10-23MLK-24914-02 plat: imx8mp: Remove the wait mode workaround used on A0Jacky Bai
The i.MX8MP A0 silicon will not be supported anymore, remove the wait mode workaround to make the cpuidle support more robust & simplify the code logic. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com>
2020-10-23MLK-24914-01 plat: imx8mp: Remove vpu reset & memrepair workaroundJacky Bai
The VPU reset & memrepair workaround is only for i.MX8MP A0 silicon. As the A0 will not be supported anymore, so drop these workaround Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com>
2020-10-22TEE-619 imx: 8mn: add support for i.MX 8MN DDR3L EVKSilvano di Ninno
DD3L EVK board only has 512MB of DDR. move OP-TEE mapping for all the 8MN boards. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-10-22MLK-24904 plat: imx: Use sc_rm_memreg_frag() to avoid memory partition overlayAnson Huang
Use sc_rm_memreg_frag() instead of sc_rm_memreg_alloc() to avoid memory partition overlay, sc_rm_memreg_frag() will return non-overlapping regions. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-10-19MLK-24897 plat: imx8m: Add dram pll setting for 3200mtsJacky Bai
Add DRAM PLL frequency setting for 3200mts. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-10-13MLK-24599 Revert "spd: opteed: enable NS_TIMER_SWITCH"Peng Fan
This cause RCU stall on i.MX platform, because timer control register was cleared to 0, and non secure timer interrupt was disabled during OP-TEE executing tests. This reverts commit 43f999a7e35db5bdbb5af6dfc7efc46f6ecab443. Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2020-09-18MLK-24812 plat: imx8mp: Assign wdog1 to domain0 onlyJacky Bai
Normally, the wdog1 is used by A53 side, and it should be stopped when A53 domain enter STOP mode. when system out of PoR, this watchdog is owned by both M7 & A53 side, then this watchdog can only enter STOP mode only when both A53 & M7 enter STOP mode. it is not reasonable as this watchdog is only used by A53 side, so assign wdog1 to domain0(a53 side) only. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-09-08MLK-24721 plat: imx8m: Fix the out of bound access to rank setting arrayJacky Bai
Fix the out of bound access to the rank setting array. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2020-08-31imx: Fix multiple definition of ipc_handleSamuel Holland
This is not conforming C and does not compile with -fno-common. Upstream-Status: Backport Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: I6535954cc567d6efa06919069b91e3f50975b073
2020-08-31imx: Fix missing inclusion of cdefs.hSamuel Holland
This was found by compiling with -fno-common: ./build/picopi/release/bl2/imx_snvs.o:(.bss.__packed+0x0): multiple definition of `__packed'; ./build/picopi/release/bl2/imx_caam.o:(.bss.__packed+0x0): first defined here __packed was intended to be the attribute macro from cdefs.h, not an object of the structure type. Upstream-Status: Backport Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Id02fac3f098be2d71c35c6b4a18012515532f32a
2020-08-18MLK-24513 plat: imx8mp: disable the memrepair clock when do domain power downJacky Bai
The memrepair clock also need to be disable before domain power down, so fix it to make sure the memrepair logic can work as expected. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com> Reviewed-by: Jian Li <jian.li@nxp.com> Tested-by: Jian Li <jian.li@nxp.com>
2020-08-14MLK-24502 plat: imx8m: Add mem repair done check for domain that need repairJacky Bai
The memory repair clock should be disabled before domain power up, and enabled after power up. need to check the memory repair done status that need memory repair. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-08-13MLK-24474: Add SIP call to enable FIPS modeFranck LENORMAND
The configuration of the FIPS alter the SoC which is configured and cannot be reverted so the support SHALL NOT be in customer binary as it could lead to DoS of the SECO. We add a SIP service to configure the FIPS mode. It is added to the ATF because it is the only component with the required permissions to successfully perform the call. This service currently only allow to set the FIPS mode with a value but can be extended. IT can be called from other components like uboot or the OS. The support is added only if the bl31 is compiled with FIPS_CONFIG defined which happens when FIPS_CONFIG=on is passed as option to Makefile. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Acked-by: Anson Huang <anson.huang@nxp.com> Acked-by: Ye Li <ye.li@nxp.com>
2020-08-13MLK-24474: Add SECO API sc_seco_set_fips_modeFranck LENORMAND
The SCFW API sc_seco_set_fips_mode allow to configure the mode of the FIPS feature on SoC. This configuration is performed on fuses and cannot be reverted. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Acked-by: Anson Huang <anson.huang@nxp.com> Acked-by: Ye Li <ye.li@nxp.com>
2020-08-11MLK-24480 plat: imx8dxl: Enable CPU/FP/L2 retention counterAnson Huang
Enable CPU, FP, L2 retention counters to 64 cycles for i.MX8DXL. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-08-03MLK-24457 plat: imx8m: Fix the current fsp initJacky Bai
The dfimisc reg value should be shift right 8 bit to get the current fsp. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-07-20MLK-24414 plat: imx8mp: Add the dsp low power audio basic supportJacky Bai
if LPA buffer is in OCRAM, then the LPA flag is 0xD, if LPA buffer is in DRAM, then the LPA flag is 0x1D. when audio buffer is in DRAM, then DRAM can be put into retention when A53 is suspended. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Tested-by: Bing Song <bing.song@nxp.com>
2020-07-01MLK-24360 plat: imx8mp: fix the vpu noc nttp handshake hang issueJacky Bai
The VC8000E's clock should be gated before power up it to make sure the noc port can be synced successfully during vc8000e reset. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-05-14MLK-23930-2 plat: imx8m: Add csu and rdc testSilvano di Ninno
re-enable csu and rdc test for use of the test team only enable if CSU_RDC_TEST is defined. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-05-14MLK-23930-1 plat: imx8mq: cleanup csu and rdc implementationSilvano di Ninno
Align CSU CSL defines with the rest of the imx8m family Compile csu and rdc drivers. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
2020-05-11MLK-23969 imx: Update SCFW API message type according to latest SCFWAnson Huang
The SCFW commit 3e500fb26979 ("SCF-621: Change pad width in sc_rm_is_pad_owned() RPC.") changes pad width in sc_rm_is_pad_owned() RPC, update it accordingly. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-05-09MLK-23821-04 plat: imx8m: Fix the rank to rank issueJacky Bai
update umctl2's setting based on phy training CDD value to workaround the rank-to-rank space issue. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-05-09MLK-23821-03 plat: imx8m: Fix the dfiphymaster setting after dvfsJacky Bai
the dfiphymaster setting need to be save/restore to make sure it aligned with the initial config. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-05-09MLK-23821-02 plat: imx8m: update the ddr4 dvfs flow to include ddr3l supportJacky Bai
the DDR3L & DDR4 can share same piece of code of DVFS, so update the ddr4 dvfs to support DDR3L too. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-05-09MLK-23821-01 plat: imx8m: Correct the rank number get from mstrJacky Bai
the bitfield of active_ranks in MSTR is defined as below. Correct the rank num get in dram_info. 0x01: one rank; 0x11: two rank; Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-05-07MA-17076 plat: imx8: Only save data section for cold rebootJi Luo
In some cases, the bl31 won't be reloaded when spl is not supported, commit 17de039 adds the save/restore data section to fix boot issues which is caused by the dirty data in data section of previous boot. However, sometimes the backup data section in dram won't be erased totally in board cold reboot, it will be restored and modify the 'correct' data section which will cause the board hang. This commit uses a global flag 'data_section_restore_flag' which is initialized as '0x1' and should be stored in data section to indicate the save/restore behavior. Test: cold/warm reboot on imx8qm/imx8qxp. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2020-04-29MLK-23870 plat: imx8mq: Correct the pll override setting after resumeJacky Bai
The anamix PLL override setting should be cleared after system resume. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-04-28MLK-23856 plat: imx8mp: remove the unnecessary power domains from the init ↵Jacky Bai
on list Only put the necessary power domain that need to on by default in the init on list Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <anson.huang@nxp.com>
2020-04-27MLK-23857 imx8mm/mn/mp: Fix DRAM MMU attribute to non-secure for HABYe Li
DRAM MMU settings miss the MT_NS on iMX8MM/MN/MP, this breaks the HAB function since we load image by u-boot in NS mode and authenticate it in ATF. Without MT_NS, ATF access secure memory which is different cacheline with non-secure memory. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
2020-04-23MLK-23805-03 plat: imx8mp: Keep audiomix always on if lpa is activeJacky Bai
Keep the audiomix power domain always on if the LPA is active & doing audio playback. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-04-23MLK-23805-02 plat: imx8mp: Fix the system wakeup setting when lpa activeJacky Bai
when LPA is active, system wakeup source still need to be configured to mask the non-wakeup irq. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
2020-04-23MLK-23805-01 plat: imx8mp: Correct the MU IRQ mask reg offsetJacky Bai
Correct the GPC IMR register offset of MU IRQ mask. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
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