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A53 core's power up ack need to be used when system resume
from DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Use non-fast wakeup stop mode for system suspend support, so
the SOC can enter DSM mode by default.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the anamix PLL override setting for DSM mode support,
so that the PLL can be power down in DSM mode to save power.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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This new workaround takes advantage of the per core IMR registers in GPC in
order to unmask the IRQ0, still generated by the 12bit in IOMUX_GPR register
(which now remains always set), so it can only wake up one core at the time.
Also, this entire workaround has now been moved here in TF-A, allowing the
kernel side to be minimal.
Another advantage this workaround brings is the removal of the 50us delay
(which was necessary before in gic_raise_softirq in kernel) by allowing the
core that is waking up to mask his own IRQ0 in the suspend finish callback.
One important change here is the way the cores are woken up in
dram_dvfs_handler. Since the wake up mechanism has changed from asserting the
12th bit in IOMUX_GPR and leaving the IMR1 1st bit on for each core to exactly
the reverse, that is, leaving the IOMUX_GPR 12th bit always set and then
masking/unmasking the IMR1 1st bit for each independent core, we need to use
the imx_gpc_core_wake to wake up the cores.
Also, the 50us udelay is moved to TF-A (inside imx_pwr_domain_off) from kernel
(gic_raise_softirq), since the new cpuidle workaround does not need it in order
to clean the IOMUX_GPC 12bit. For now, the udelay seems to be still needed
in order to delay the affinity info OFF for the dying core. This is something
that needs further investigation.
Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the dram retention support for i.MX8MQ. As there is
no enough ocram space available before entering TF-A,
so the timing info need to be copied from dram into ocram.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Move the stack & xlat table into ocram_s due to the
ocram is not enough.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the CSU init on i.MX8MN & config the ocram
secure access range. CSU config for specific
system design can be added in the 'csu_cfg' array.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Enable the CSU init on imx8mm. The 'csu_cfg' array
is just a placeholder for now as example. In real
use case, user can add the CSU config as needed
based on system design.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add a simple CSU driver for i.MX8M family.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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CPU hotplug & cpuidle have some race condition when doing CPU hotplug
stress test. different CPU cores have the chance to access the same
GPC register(A53_AD), so lock is necessary to do exlusive access.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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After the SRC bit clear, we must wait for a while to make sure
the operation is finished. And don't enable all the PU domains
by default.
for USB OTG, the limitations are:
1. before system clock configuration. ipg clock runs at 12.5MHz.
delay time should longer than 82us.
2. after system clock configuration. ipg clock runs at 66.5MHz.
delay time should longer than 15.3us.
so add udelay 100 to safely clear the SRC bit 0.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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No need to keep all PU domains on as the full power domain driver
support has been added.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the PU power domain support for imx8mm/mn.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add PLL power down override & bypass support when
system enter DSM mode.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Keep A53 PLAT(SCU) power domain on in wait mode(ret).
RBC count only need to be set in PLAT OFF mode, so
change it accordingly.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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On iMX8 Rev A the OCRAM is used to pass over ROM info, and u-boot
needs to access it. So we can't assign the OCRAM to ATF partition.
This will cause boot hang.
Rev A does not support SPL, so it is ok to not protect the OCRAM.
Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit c9a168bfd16e06b4d6b9f94185910023e4923cf2)
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Because the partition reboot won't reload the first level bootloader (SPL),
the SPL won't be authenticated. Users can corrupt the SPL image to break
the boot trust chain in secure boot if we don't protect that OCRAM area.
This patch configures the memory area from 0x0 to 0x118000 only accessed by
secure partition (ATF and OPTEE). Non-secure partitions (u-boot and kernel)
can't access it.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit 1eff7d3ef6f121782e56bb1807744ede48b8580b)
(cherry picked from commit 96d33120bb57895db73e669ef0aeccde0d4875d5)
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Sync SCFW API to commit b3c575a62b0e2
SCFW API version 16
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
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Update flags for expected behavior in ATF
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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Add the DDR frequency change support.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I84f0ef51b04b84da8ba2cbeca86a07338a4903de
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Enable dram retention support on i.MX8MN.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Enable dram retention support on i.MX8MM.
Change-Id: I76ada615d386602e551d572ff4e60ee19bb8e418
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the dram retention flow for i.MX8M SoC family.
Change-Id: Ifb8ba5b2f6f002133cf47c07fef73df29c51c890
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add imx8mn basic support
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Each memory region slot occupies 16bypte space, so
correct the the offset of config register address.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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For platform CONFIGs, platform name should use lower case.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Normally, SGI6 & SGI7 is used by non-secure world, these
two SGIs should not be reserved for secure interrupt purpose.
On i.MX8M platform, SGI8 is used for secure group0 IPI for
DDR DVFS, So update the code to reserve SGI8 for secure world.
Change-Id: Ib1ed9786e0a79bb729b120a0d4d791d13b6f048a
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
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Add the basic support for opteed SPD on imx8mq & imx8mm.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I6c4855c89dea78d13d172c3d86cf047f829e51ce
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With SPL running on OCRAM, when linux suspend, OCRAM
will lose power and if partition reboot is started from
SPL, system will hang as the OCRAM data lost, so for
partition reboot, the CPU boot entry can be set to
be from ATF BL31 entry directly, SCFW exposes such API
for this scenario.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add pwr_domain_pwr_down_wfi callback for i.MX8QM.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add pwr_domain_pwr_down_wfi callback for i.MX8QX.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Sync SCFW API to commit 6dcd0242ae
Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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As per design team's suggestion, L2 cache's ECC & parity
should be enabled for A72 cluster.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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SC_R_GIC_SMMU is a master resource, we can't set peripheral
permission to this resource, otherwise the API will return below error
on latest SCFW, because SCFW has added a resource type check.
On old SCFW, the API does nothing to a master resource. So remove the
resource from ns_access_allowed array.
ERROR: sc_rm_set_peripheral_permissions: rsrc 14, ret 3
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add system_reset2 support for i.MX8QM/i.MX8QX to support
WARM/COLD/BOARD reset.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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MU_SR register bit[30] is cold boot flag passed from SCU,
w0 is random value and would clear the flag incorrectly,
and cause system partition reboot fail if Linux is in suspend.
So this patch initializes it to 0x80000000 which is exactly
the same with first time board power up before writting to MU_SR
register.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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With partition reboot enabled, console_list variable which is
located in data section is NOT reset, system will be busy looping
in early console operation of flush_loop() if console_list is
NOT 0 while HW console is NOT initialized, so we have to clear
this variable to make partition reboot work.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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The issue of A53 cluster runtime power ON/OFF has been
identified as fifo reset issue, and there is software
workaround to avoid such issue and A53 cluster now can
be turned OFF.
Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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GICR_WAKER.ProcessorSleep can only be set to zero when:
— GICR_WAKER.Sleep bit[0] == 0.
— GICR_WAKER.Quiescent bit[31] == 0.
On some platforms, when system reboot with GIC in sleep
mode but with power ON, such as on NXP's i.MX8QM, Linux
kernel enters suspend but could be requested to reboot,
and GIC is in sleep mode and it is inside a power domain
which is ON in this scenario, when CPU reset, the GIC
driver trys to set CORE's redistributor interface to awake,
with GICR_WAKER.Sleep bit[0] and GICR_WAKER.Quiescent bit[31]
both set, the ProcessorSleep bit[1] will never be clear
and cause system hang.
This patch makes sure GICR_WAKER.Sleep bit[0] and
GICR_WAKER.Quiescent bit[31] are both zeor before clearing
ProcessorSleep bit[1].
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Due imx8qm_mek's UART0_RTS_B and UART0_CTS_0 pad
reuse to be the UART2 for base bard which operated by
M4_1, so don't touch these two pads in ATF.
Signed-off-by: Haoran.Wang <elven.wang@nxp.com>
Acked-by: Pete Zhang <pete.zhang@nxp.com>
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With flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr.
However after m4 core moved to non-secure partition, the ddr memory
is still in secure partition. Then m4 core will fault.
So postpone moving resources including m4 core, until other resources,
such as memory/pin moved to non-secure partition.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd)
(cherry picked from commit 5b026e05b8f71b3d86da0953c5ca196d5ba5cc66)
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With default configuration, M4 and A35 in one partition, M4 is loaded by ROM.
"err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);"
M4 core will first be moved to non-secure OS part, then the resource used
by M4 will be moved to non-secure OS part later. But before the resource be
moved to non-secure OS part, M4 core is still running, so a non-secure M4
core access a secure resource will trigger error in M4 side.
First mark M4 core as non-movable, after all other resoures moved to OS
part, move M4 to OS part. No need to check whether M4 is created a new
partition by SCFW, if a partition already created, the call to mark
M4 as non-removable will fail, because it M4 is in its own partition.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
(cherry picked from commit 44e209cb87f078abc78839c5e138aae5122ddd78)
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Since we use ATF version string to provide commit id, we must ensure
the commit id is in this string. But when a commit is tagged, the
git describe will default output the tag string. Add the '--long' option
to output a full string with commit id contained.
Signed-off-by: Ye Li <ye.li@nxp.com>
(cherry picked from commit c80009f7c58534b257892f0bca168fd187779e58)
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Add tzc380 debug support.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Test if a partition reboot has taken place with the MU
interrupt bit. Check before returning the entrypoint
Signed-off-by: Teo Hall <teo.hall@nxp.com>
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NXP's i.MX8 SoCs with system controller inside support outputting
debug message to system controller's console via calling SCFW API,
since TF-A shares debug console with Linux kernel which will have
confliction if Linux kernel and TF-A's console are both enabled,
this patch adds support for switching TF-A debug console to system
controller to easy TF-A debug.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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For NXP's SoCs with system controller inside, partition reboot
is supported in SCFW, change the system reset API from board reset
to partition reboot, so each partition can reboot independently.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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Add WDOG functions SIP support.
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
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