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2017-07-12Correct debug uart baudrate for i.MX8QMAnson Huang
UART baudrate is 115200 on i.MX8QM ARM2 board. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12PSCI: support killing offline CPUAnson Huang
When secondary CPUs are offline, some platforms do NOT support shutting down secondary CPUs by themself, need to use other online CPU to shutdown those CPUs which are being offline, this patch adds killing offline CPUs. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2017-07-12Add i.MX8QXP supportAnson Huang
Add i.MX8QXP platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
2017-07-12Add i.MX8QM suport.Anson Huang
Add i.MX8QM platform support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add i.MX8 SoCs supportAnson Huang
This patch adds i.MX8 SoCs ATFW support, including below basic features: * LPUART * SCFW RPC * SMP boot up Each SoC will have its own platform definition and driver to support. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add interface for enabling wake up from WFI in EL3Anson Huang
Add interface to enable FIQ routing in SCR_EL3 to make interrupts can wake up ARM from WFI when executing in EL3, as all interrupts are signaled as FIQ in EL3. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-12Add necessary type definitionsAnson Huang
Add bool/true/false type to make it easy for porting code from other platforms. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2017-07-07Merge pull request #1025 from davidcunado-arm/dc/version_updatedavidcunado-arm
Release v1.4: Update minor version number to 4
2017-07-07Merge pull request #1026 from eleanorbonnici-arm/eb/OoB_testdavidcunado-arm
Updates user guide following out of box testing.
2017-07-07Updates user guide following out of box testing.Eleanor Bonnici
Change-Id: I0cd355d9fc7f14fb4eabb443d596d6f0858f609e Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com>
2017-07-06Merge pull request #1022 from danh-arm/dh/v1.4-readmedavidcunado-arm
Update readme for v1.4 release
2017-07-06Release v1.4: Update minor version number to 4David Cunado
Change-Id: I8676a22649dce92d0ddd98013fc6dafcfbe94c90 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-07-06Merge pull request #1024 from davidcunado-arm/dc/update_userguidedavidcunado-arm
Release v1.4: update change-log.rst
2017-07-06Release v1.4: update change-log.rstDavid Cunado
Updated change-log.rst with summary of changes since release v1.3. Change-Id: Iecd31ed315bd9ad7ffe8bce6550f7c90e1e3a9b0 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-07-06Merge pull request #1023 from davidcunado-arm/dc/update_userguidedavidcunado-arm
Migrate to Linaro release 17.04
2017-07-06Migrate to Linaro release 17.04David Cunado
ARM TF has been tested against Linaro Release 17.04 - the Linaro binaries have been update and also the version of the compiler. Linaro binaries: 17.01 --> 17.04 AArch64 & AArch32 compilers: 5.3-2015.05 (gcc 5.3) -> 6.2-2016.11 (gcc 6.2) This patch updates the User Guide is to state that Linaro release 17.04 is supported. Additionally, the following fixes are made to the User Guide: - Removed out of date reference to Linaro release 16.06. - Updated the Juno variant coverage to include r2. Change-Id: Iebbced3356f8c6b3c2bff2df62574db9f937ca7b Signed-off-by: David Cunado <david.cunado@arm.com>
2017-07-06Merge pull request #1010 from davidcunado-arm/dc/update_userguidedavidcunado-arm
Update Foundation, AEM and Cortex Models versions
2017-07-05Update readme for v1.4 releaseDan Handley
Update the release notes (readme.rst) for the ARM Trusted Firmware v1.4 release. Also, reorder and fix some of the links following the conversion to reStructured text format. Change-Id: I8f5e8aa86cb891f61b6b62cf9fab0ad0f0ebb36b Signed-off-by: Dan Handley <dan.handley@arm.com>
2017-07-05Update Foundation, AEM and Cortex Models versionsDavid Cunado
Trusted Firmware has been tested as part of its CI system against Cortex and Foundation models in the 11.0 Model release available on developer.arm.com. Trusted Firmware has also been tested against the v8.5 AEM model. This patch updates the user guide documentation to reflect the version of the Foundation, AEM and Cortex Models that Trusted Firmware has been tested against. Change-Id: I3b5b4d1e4220bda1dcc88aa9cfa01fa711ed92cd Signed-off-by: David Cunado <david.cunado@arm.com>
2017-07-05Merge pull request #1011 from douglas-raillard-arm/dr/doc_convert_to_rstdanh-arm
Convert Markdown to reStructuredText
2017-06-29Remove Markdown documentationDouglas Raillard
Removed Markdown documents as they have been converted to reStructuredText. Change-Id: I3148222eb31258f158f64de4ddcdda4b232ce483 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-29Manual fixes to reST documentationsDouglas Raillard
Non-automated fixes to the converted documentation. Change-Id: I61f3d37c7a8d6a56a7351048060b970c5b3751e4 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-29Convert documentation to reStructuredTextDouglas Raillard
Due to recent issues in the rendering of the documentation on GitHub and some long-standing issues like the lack of automatic table of content in Markdown, the documentation has been converted to reStructuredText. Basic constructs looks pretty similar to Markdown. Automatically convert GitHub markdown documentation to reStructuredText using pandoc. Change-Id: If20b695acedc6d1b49c8d9fb64efd6b6ba23f4a9 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-29Fix various small issues in the documentationDouglas Raillard
Change some hard-to-convert constructs to cleaner ones. Fix a broken link. Change-Id: Ida70aa1da0af7a107b0e05eb20b8d46669a0380b Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-28Merge pull request #1007 from soby-mathew/sm/ccintdanh-arm
Enable integration of ARM TrustZone Cryptocell for TBB
2017-06-28Use CryptoCell to set/get NVcounters and ROTPKSoby Mathew
This patch implements the platform APIs plat_get_rotpk_info, plat_get_nv_ctr, plat_set_nv_ctr to invoke CryptoCell SBROM APIs when ARM_CRYPTOCELL_INT is set. Change-Id: I693556b3c7f42eceddd527abbe6111e499f55c45 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Do basic CryptoCell LCS checkSoby Mathew
This patch implements the basic lifecycle state check when CryptoCell SBROM is initialized. Currently the check ensures that if the lifecycle state is Security Disabled (SD), the boot process does not proceed further. Change-Id: I5101335453cd3ea413e97bcfb9138a96c05e1aea Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28ARM plat changes to enable CryptoCell integrationSoby Mathew
This patch makes the necessary changes to enable ARM platform to successfully integrate CryptoCell during Trusted Board Boot. The changes are as follows: * A new build option `ARM_CRYPTOCELL_INTEG` is introduced to select the CryptoCell crypto driver for Trusted Board boot. * The TrustZone filter settings for Non Secure DRAM is modified to allow CryptoCell to read this memory. This is required to authenticate BL33 which is loaded into the Non Secure DDR. * The CSS platforms are modified to use coherent stacks in BL1 and BL2 when CryptoCell crypto is selected. This is because CryptoCell makes use of DMA to transfer data and the CryptoCell SBROM library allocates buffers on the stack during signature/hash verification. Change-Id: I1e6f6dcd1899784f1edeabfa2a9f279bbfb90e31 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Add CC crypto driver to the Auth moduleSoby Mathew
This patch adds a crypto driver which utilizes the ARM® TrustZone® CryptoCell-712 to verify signature and hash during Trusted Board Boot. Along with this driver, the CryptoCell SBROM library is required to successfully build the BL image. The path to this library is specified via the `CCSBROM_LIB_PATH` variable. Please note that, mbedTLS is still required to do the X509 certificate ASN.1 parsing and CryptoCell is only utilized for signature and hash verification. Change-Id: If82dfbae0d7772ba1c64839f0b27850c103fe253 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Add headers to enable CryptoCell integrationSoby Mathew
This patch adds header files with required declarations and macro definitions to enable integration with CryptoCell SBROM version `CC712 – Release 1.0.0.1061`. These headers enable ARM Trusted Firmware to build and link with CryptoCell SBROM library. Change-Id: I501eda7fe1429acb61db8e1cab78cc9aee9c1871 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Add support to link an external lib with ARM TFSoby Mathew
This patch defines the variable `LDLIBS` which allows external libraries to be specified to 'ld' to enable it to link the libraries. Change-Id: I02a490eca1074063d00153ccb0ee974ef8859a0e Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-28Merge pull request #1008 from douglas-raillard-arm/dr/add_TF_LDFLAGSdanh-arm
Introduce TF_LDFLAGS and improve CFLAGS documentation
2017-06-28Document CFLAGS make optionDouglas Raillard
CFLAGS content can be set on the command line to allow passing extra options to the compiler. Its content is appended after the options set by the Makefile (TF_CFLAGS). The Makefiles must use TF_CFLAGS instead of CFLAGS, as the latter can be completely overriden by setting it on the command line. Also tell about LDFLAGS in the "Debugging options" section. Change-Id: Iaf27b424002898ef3040133f78cb133983a37aee Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-28Introduce TF_LDFLAGSDouglas Raillard
Use TF_LDFLAGS from the Makefiles, and still append LDFLAGS as well to the compiler's invocation. This allows passing extra options from the make command line using LDFLAGS. Document new LDFLAGS Makefile option. Change-Id: I88c5ac26ca12ac2b2d60a6f150ae027639991f27 Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-28Merge pull request #1009 from islmit01/im/aarch32_junodanh-arm
Add Juno AArch32 and AArch64 User Guide instructions
2017-06-28Add Juno AArch32 and AArch64 User Guide instructionsIsla Mitchell
Updated section 6, building a FIP for Juno and FVP, adding instructions for AArch32 and AArch64. Updated section 4.1, summary of build options, to include a description of the `JUNO_AARCH32_EL3_RUNTIME` build flag. Change-Id: I4ed006522cab981371c382859063f088fbfcb8f7 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
2017-06-28Merge pull request #1006 from robertovargas-arm/doc-formatdanh-arm
Improve format of exception vectors in BL1 description
2017-06-28Merge pull request #1004 from rockchip-linux/erratum-rk3399danh-arm
rockchip: enable A53's erratum 855873 for rk3399
2017-06-28Merge pull request #1003 from douglas-raillard-arm/dr/doc_fix_broken_linkdanh-arm
Fix broken link in documentation
2017-06-28Merge pull request #1002 from douglas-raillard-arm/dr/fix_errata_a53danh-arm
Apply workarounds for A53 Cat A Errata 835769 and 843419
2017-06-28Merge pull request #1001 from davidcunado-arm/dc/fix-signed-comparisonsdanh-arm
Resolve signed-unsigned comparison issues
2017-06-28Merge pull request #978 from etienne-lms/minor-builddanh-arm
Minor build fixes
2017-06-28Improve format of exception vectors in BL1 descriptionRoberto Vargas
Without the additional newlines all the text becomes a single paragraph and next newlines are ignored. Change-Id: I783198477f654e3923fcabb21248f2bc62c33e9d Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
2017-06-28rockchip: enable A53's erratum 855873 for rk3399Caesar Wang
For rk3399, the L2ACTLR[14] is 0 by default, as ACE CCI-500 doesn't support WriteEvict. and you will hit the condition L2ACTLR[3] with 0, as the Evict transactions should propagate to CCI-500 since it has snoop filters. Maybe this erratum applies to all Cortex-A53 cores so far, especially if RK3399's A53 is a r0p4. we should enable it to avoid data corruption, Change-Id: Ib86933f1fc84f8919c8e43dac41af60fd0c3ce2f Signed-off-by: Caesar Wang <wxt@rock-chips.com>
2017-06-27Merge pull request #1000 from dp-arm/dp/aarch32-bootdavidcunado-arm
juno/aarch32: Fix boot on Cortex A57 and A72
2017-06-27Fix broken link in documentationDouglas Raillard
Fix link in docs/firmware-update.md and docs/change-log.md: https://github.com/ARM-software/arm-trusted-firmware/wiki/ARM-Trusted-Firmware-Image-Terminology Change-Id: I2d51d373fd0f7da59b548cd6bed52c47772014fd Signed-off-by: Douglas Raillard <douglas.raillard@arm.com>
2017-06-27Resolve signed-unsigned comparison issuesDavid Cunado
A recent commit 030567e6f51731982a7e71cbd387de93bc0e35fd added U()/ULL() macro to TF constants. This has caused some signed-unsigned comparison warnings / errors in the TF static analysis. This patch addresses these issues by migrating impacted variables from signed ints to unsigned ints and vice verse where applicable. Change-Id: I4b4c739a3fa64aaf13b69ad1702c66ec79247e53 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-27Merge pull request #999 from douglas-raillard-arm/dr/fix_tegra_CFLAGSdavidcunado-arm
Fix Tegra CFLAGS usage
2017-06-26juno: Invalidate all caches before warm reset to AArch32 state.Dimitris Papastamos
On Juno AArch32, the L2 cache may contain garbage after the warm reset from AArch64 to AArch32. This is all fine until the MMU is configured and the data caches enabled. To avoid fetching stale data from the L2 unified cache, invalidate it before the warm reset to AArch32 state. Change-Id: I7d27e810692c02c3e83c9f31de67f6bae59a960a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-26juno/aarch32: Restore `SCP_BOOT_CFG_ADDR` to the cold boot valueDimitris Papastamos
Before BL2 loads the SCP ram firmware, `SCP_BOOT_CFG_ADDR` specifies the primary core. After the SCP ram firmware has started executing, `SCP_BOOT_CFG_ADDR` is modified. This is not normally an issue but the Juno AArch32 boot flow is a special case. BL1 does a warm reset into AArch32 and the core jumps to the `sp_min` entrypoint. This is effectively a `RESET_TO_SP_MIN` configuration. `sp_min` has to be able to determine the primary core and hence we need to restore `SCP_BOOT_CFG_ADDR` to the cold boot value before `sp_min` runs. This magically worked when booting on A53 because the core index was zero and it just so happened to match with the new value in `SCP_BOOT_CFG_ADDR`. Change-Id: I105425c680cf6238948625c1d1017b01d3517c01 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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