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2018-11-28plat: imx8qm/imx8qxp: Add MU flag check for partition rebootimx_4.14.78_1.0.0_gaTeo Hall
Test if a partition reboot has taken place with the MU interrupt bit. Check before returning the entrypoint Signed-off-by: Teo Hall <teo.hall@nxp.com> (cherry picked from commit 627396daa5d9b62e8a0fb118844d1507b94e23f5)
2018-11-26TEE-330-4: i.MX8QM: OP-TEE: Pass boot info to u-bootSilvano di Ninno
If ATF loads OP-TEE, it will pass OP-TEE base address and size to the u-boot through boot information. This will help u-boot update device tree accordingly. Note that u-boot on i.MX 8QxP does not need this information to configure memory mapping. Query to the SC Firmware is used instead. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 70c1d422e520f8f1c201a7e4fe22870832240db7)
2018-11-26TEE-330-3: i.MX8QM: OP-TEE add share memorySilvano di Ninno
Configure OP-TEE Share memory to be accessible by OS. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit b2d0c8530c75bb77450372114229cadd8555780b)
2018-11-26TEE-330-2: i.MX8QM: TEE Fix BL32_SIZESilvano di Ninno
Fix size of BL32 (currently is 32MB). Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 5087a9cda77b3c6a5566e4a9520ab476bfe9154a)
2018-11-26TEE-330-1: OP-TEE: Add support for i.MX 8QMSilvano di Ninno
Reuse Trusty support for OP-TEE Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit a558c8fb87171f4ebcc44bb0b8aa699c989a2a7d)
2018-11-26TEE-329-4: OP-TEE: Pass boot info to u-bootSilvano di Ninno
If ATF loads OP-TEE, it will pass OP-TEE base address and size to the u-boot through boot information. This will help u-boot update device tree accordingly. Note that u-boot on i.MX 8QxP does not need this information to configure memory mapping. Query to the SC Firmware is used instead Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit e80fe229192578120a3ba98ae26fd3dbf121538f)
2018-11-26TEE-329-3: OP-TEE add share memorySilvano di Ninno
configure OP-TEE Share memory to be accessible by OS. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 0b5eeb7e0dbe50ebd7f3d0ce66047569504e9d52)
2018-11-26TEE-329-2: Fix BL32_SIZESilvano di Ninno
fix size of BL32 (currently is 32MB) Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit f66251dedef31750ff7be4c0e404b77d0a8fb1c4)
2018-11-26TEE-329-1: OP-TEE: Add support for i.MX 8QxPSilvano di Ninno
reuse Trusty support for OP-TEE Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> (cherry picked from commit 6e2885a262b94bdeb8face851012f58ed32e86a9)
2018-11-13MMIOT-180: ddr address is 33bit width, but rdc memory region register is ↵Olivier Masse
32bit. So we use [32:1] as the configuration value Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-11-13MMIOT-152 + MMIOT-157 : move specific RDC configuration from driver to board ↵Olivier Masse
setup Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-11-13MMIOT-152 Rebase on imx_1.5.y + imx8mm : DRM RDC config addedOlivier Masse
Signed-off-by: Olivier Masse <olivier.masse@nxp.com>
2018-11-13MLK-20238-02 plat: imx8m: initialized the value before useBai Ping
Fix Coverity CID 5209712: Uninitialized scalar variable (UNINIT) issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-13MLK-20238-01 plat: imx: fix uninitialized value usingBai Ping
fix Coverity: CID 5243766: Uninitialized scalar variable (UNINIT) issue. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-03plat: imx8mq: fix boot hang if no valid dram infoBai Ping
If no valid dram info to copy from DRAM, skip copy the dram info. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02plat: imx8mq: remove unused files on imx8mqBai Ping
remove unused files on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-02plat: imx8mq: refact the dram low power codeBai Ping
refact the dram low power related code to make it more friendly for different dram config or different board. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-01plat: imx: Add sw workaround for the VPU&GPU resetBai Ping
ERR050044: GPU/VPU power domain on/off stress test leads to unexpected GPU interrupts and hang. his is caused by no dedicated HW resets for GPU2D/3D. There is one reset for whole GPUmix and GPU2D/3D has their own SW reset signals. The SW reset cannot be asserted while GPU2D/3D is in power off status. So if only GPU2D or GPU3D has to be powered off and on, unknown status leads to the problem. VPU has similiar issue. So we need to assert the SW reset before power up the power domain. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-11-01imx8q: [trusty] Kick CAAM powerJi Luo
JR0 and JR1 of CAAM are owned by SECO, only kick the power of JR2 and JR3 here and assign the resources to be accessed by secure world. Signed-off-by: Ji Luo <ji.luo@nxp.com>
2018-10-29MA-13239 imx8qm: Touch correct pad for UART0Haoran.Wang
Due imx8qm_mek's UART0_RTS_B and UART0_CTS_0 pad reuse to be the UART2 for base bard which operated by M4_1, so don't touch these two pads in ATF. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Acked-by: Pete Zhang <pete.zhang@nxp.com>
2018-10-25iMX8Q: Don't copy tee after fit is enabledLuo Ji
Tee(Trusty Os) will be stored in fit for Android and Android Auto so we don't need to copy it anymore, this will save some boot time. Signed-off-by: Luo Ji <ji.luo@nxp.com>
2018-10-25MLK-20044 plat: imx8m: fix ddr4 dvfs hang after retentionBai Ping
The RFSHCTL3.refresh_mode should be set normal mode if we want to disable auto refresh mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-23imx8qxp: add support for cpuidleAnson Huang
This patch adds support for cpuidle with CPU powerdown, there will be 3 idle states in Linux kernel: 1: wfi; 2: cpu power down; 3: cluster power down. As Linux kernel needs a broadcast timer for waking up CPU when whole CLUSTER is powerdown, GPT is adopted as broadcast timer, and to make the clock & power management easy for Linux kernel to avoid many workaround/hake in Linux kernel, TF-A will handle GPT's power & clock management as well as registers save/restore when suspend/resume. Also, psci power states are used to determine CORE/CLUSTER/SYSTEM power state to distinguish CPU idle and SYSTEM suspend which share same domain_suspend callback. The SoC IPs register mmap regions are merged into 1 large section to cover all the SoC IPs register ranges TF-A needs, this is to save mmap regions and make it simple. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-10-12plat: imx8m: update the DVFS flow for DDR4Bai Ping
Update the DDR4 DVFS flow Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-12imx8m: Add DDR4 DVFS supportBai Ping
Add DDR4 DVFS support for i.MX8M. Currently, only tested on i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-10-12imx8qm: keep A53 cluster power on for cache coherency issueAnson Huang
A53 cluster cannot be power gated unless the entire multi-cluster (A53 + A72 + CCI) is gated off. Root cause still TBD, this patch adds temporary workaround to ONLY allow A53 power off when system suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-10-01imx8mm: Add ddr4 retention support for imx8mBai Ping
Add ddr4 retention flow for imx8m. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-28imx8qm/imx8qxp: enable output debug message to SC consoleAnson Huang
Add support for enabling output debug message to SC console, SC_CONSOLE is used to enable/disable it. Example log output on SC console as below: *** Debug Monitor *** >$ NOTICE: smc_fid is c2000003 imx_pwr_domain_on cluster_id 0, cpu_id 1 cluster:0 core:1 is on imx_pwr_domain_on cluster_id 0, cpu_id 2 cluster:0 core:2 is on imx_pwr_domain_on cluster_id 0, cpu_id 3 cluster:0 core:3 is on imx_pwr_domain_on cluster_id 1, cpu_id 0 cluster:1 core:0 is on imx_pwr_domain_on cluster_id 1, cpu_id 1 cluster:1 core:1 is on Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-26imx8qm/imx8qxp: add misc set temp SIP supportAnson Huang
Add FSL_SIP_MISC_SET_TEMP support for setting thermal alarm function. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-18SCR-imx-atf.txt: deleted SCR since it is no longer needed.Ann Thornton
Signed-off-by: Ann Thornton <ann.thornton@nxp.com>
2018-09-17plat: imx8mq: add 100us delay after USB OTG SRC bit 0 clearBai Ping
After the SRC bit clear, we must wait for a while to make sure the operation is finished. for USB OTG, the limitations are: 1. before system clock configuration. ipg clock runs at 12.5MHz. delay time should longer than 82us. 2. after system clock configuration. ipg clock runs at 66.5MHz. delay time should longer than 15.3us. so add udelay 100 to safely clear the SRC bit 0. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-15plat: imx8mm: Add support for imx8mm lpaAnson Huang
For i.MX8MM low power audio playback, when Linux suspend, M4 still needs to be active for audio playback, so system can NOT enter DSM mode but only force A core platform into STOP mode, PLLs/NoC/DRAM need to be active as well and MU interrupt wakeup needs to be enabled for waking up Linux by MU message sent by M4. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-13imx8mq: fix soc_id issueAnson Huang
The chip revision should ONLY overwrite the lower 16 bits of soc_id, otherwise, the cpu_is_imx8mq() API in Linux kernel will be incorrect. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-12MA-11015 Support Trusty OS on imx8qm/qxpHaoran.Wang
The Trusty OS binary will be installed into container.img and loaded into 0x84000000. Due Trusty OS addresss is in 0xfe000000 which ROM cannot reach, so use ATF to copy it into the target address. Mapped the BL32 code into MMU due the Trusty SPD need to check the code status and decide the CPU executing mode. To reserve and protect the memory for secure world, modify the partition code to keep BL32 spaces in secure_part. Signed-off-by: Haoran.Wang <elven.wang@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com>
2018-09-11plat: imx8mm: fix the gpumix vpumix power downBai Ping
the GPU/VPU mix power off is skip in previous code, so correct to make sure GPU/VPU mix is actually power off. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-08imx8qm/imx8qxp: support random CPU resume when system suspendAnson Huang
Using sc_pm_set_cpu_resume API instead of sc_pm_set_cpu_resume_addr to support random CPU resume for system suspend, as Linux kernel now supports non CPU0 suspend, we have to specify the CPU ID for SCFW to wake up when system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-09-07plat: imx8mm: Read mode register setting from ddrcOliver Chen
Read the mode register setting from the DDRC, then we can make the DVFS flow more indepent from the actual DDR config. Signed-off-by: Oliver Chen <Oliver.Chen@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-09-06MLK-19465 imx8mq: Fix cpu rev issue on B0.1 chipYe Li
On B0.1 chip, the value is 0x1020 not 0x20, due to minor version updated. So if reading the word and comparing with 0x20, the result is wrong. Fix the issue by only reading low major version byte for ROM version Signed-off-by: Ye Li <ye.li@nxp.com>
2018-09-03imx8mq: update chip revision method for B1Anson Huang
i.MX8MQ B1's chip revision is identified by reading OCOTP offset 0x40, the magic number 0xff0055aa is for B1. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-31plat: imx8mq: update the ddr controller perf QoS settingBai Ping
update the ddr controller perf QoS setting on i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-27MLK-18619: [MX8MM-EVK]CSU_RDC: enable csu_rdc test in ATF make the board crashFranck LENORMAND
csu_rdc test in ATF makes use of GPIO 4 and 5. Unfortunatly GPIO5 is being used by u-boot. This is why u-boot crashes. Changing the peripherals to protect, instead of gpio4 and 5, use csu and rdc registers instead. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com>
2018-08-27imx8qm: put IRQ_STEER/DRC/DBLOGIC into OFF when suspendAnson Huang
To support KS1, need to put all resources into OFF mode instead of STBY when Linux kernel suspend. Here, DRC, IRQ_STEER and DBLOGIC can be OFF for KS1 mode. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-22imx8mq:plat: add noc priority configuration entryZhang Bo
Add NOC configuration entry for all the module. Kernel can configure the noc priority through this entry. Signed-off-by: Zhang Bo <bo.zhang@nxp.com>
2018-08-21MLK-19263 imx8m: hab: Add check target and failsafe sip callYe Li
imx_v2018.03 u-boot uses ROM's APIs: check_target and failsafe. So for iMX8M platforms, we have to implement the sip calls and use ATF to call them when u-boot running at non-secure world. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-08-21plat: imx8mm: fix system resume hang when tz380 is enabledBai Ping
If NOC is power down in DSM mode, the tz380 register config will be lost, so we must re-init the tz380 after system resume. the tz380 initialization must be done after DRAM has been out of retention. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-20MLK-19256 plat: imx8mm: correct dram apb clock rate dvfsBai Ping
The DRAM APB bus clock rate is wrong before and after DVFS. The register offset for APB bus clock is wrong, so fix it. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-08-15imx8qxp: put DRC into OFF mode when Linux suspendAnson Huang
SCFW has supported DDR retention, so now DRC can be into OFF mode instead of STBY when Linux suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-08-02plat: imx8mm: enable noc power down supportBai Ping
enable NOC power down in DSM mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-26imx8: postpone moving resources to non-secure partitionPeng Fan
With flash_uboot_cm4ddr in imx-mkimage, the m4 code will access ddr. However after m4 core moved to non-secure partition, the ddr memory is still in secure partition. Then m4 core will fault. So postpone moving resources including m4 core, until other resources, such as memory/pin moved to non-secure partition. Signed-off-by: Peng Fan <peng.fan@nxp.com> (cherry picked from commit 1c8ce0ad5f583ec41026d4ab5bef622f1b45aecd)
2018-07-26plat: imx8mm: enable power domain supportBai Ping
Enable the power domain support on imx8mm. Signed-off-by: Bai Ping <ping.bai@nxp.com>
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