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2018-07-20plat: imx8mm: Add lpddr4 dvfs supportBai Ping
add LPDDR4 DVFS support on imx8mm. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-20plat: imx: refact the dram retention flow on imx8mmBai Ping
All the DRAM timing related config is saved by SPL in OCRAM_S, so no need to do save for these configs in ATF anymore. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-20PLAT: imx: Change the bl31 base address to 0x920000 for imx8mmBai Ping
On i.MX8MM, the OCRAM's last 128K is dedicated for ATF, so move bl31 to this memory region. BuildInfo: - IMX-MKIMAGE: ee5ad91b Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-05imx8mq/imx8mm: make sure no overlap during memory mapAnson Huang
The debug version of TF-A has below assert, fix it by making sure no memory map overlap. ASSERT: lib/xlat_tables/xlat_tables_common.c:129 Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-05imx8mq/imx8mm: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-05Fix MISRA Rule 5.1Daniel Boulby
Rule 5.1: External identifiers shall be distinct Some of the identifier names in the GICv3 driver were so long that the first 31 characters were identical. This patch shortens these names to make sure they are different. Fixed for: LOG_LEVEL=50 PLAT=fvp Change-Id: Iecd551e3a015d144716b87b42c83dd3ab8c34d90 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
2018-07-05gicv3: Fix support for systems without secure interruptsAndre Przywara
Accessing the interrupt_props array only happens inside a loop over interrupt_props_num, so the GICv3 driver can cope with no secure interrupts. This allows us to relax the asserts that insists on a non-NULL interrupt_props pointer and at least one secure interrupt. This enables GICv3 platforms which have no need for a secure interrupt. This only covers the non-deprecated code paths. Change-Id: I49db291906512f56af065772f69acb281dfbdcfb Signed-off-by: Andre Przywara <andre.przywara@arm.com>
2018-07-05imx8qm/imx8qxp: switch to MULTI_CONSOLE_API for debug uart supportAnson Huang
Switch to MULTI_CONSOLE_API to make debug UART work. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-07-04plat: imx: fix boot hang on imx8mm ddr4 boardBai Ping
skip init the dram info if the ddr type is DDR4, support for it will be added later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-07-03MLK-18732-2: Add OTP SIP service for QM/QXTeo Hall
Add SIP service for OTP reading/writing for use in u-boot Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-07-03MLK-18732-1: Update to the latest SCFW APITeo Hall
Update API based on following commit: commit 24fa33d2f95707e739f01cc04d38a62bec707ceb Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Thu Jun 28 15:00:03 2018 -0500 SCF-105: Add disclaimer to docs. Signed-off-by: Chuck Cannon <chuck.cannon@nxp.com> For use of the misc otp service Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-21imx: enable necessary erratas for A53 r0p4Anson Huang
This patch enables necessary erratas for A53 r0p4 according to docs/cpu-specific-build-macros.rst. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-21Merge pull request #1397 from dp-arm/dp/cortex-a76Dimitris Papastamos
Add support for Cortex-A76 and Cortex-Ares
2018-06-21Merge pull request #1405 from dp-arm/dp/cve_2017_5715Dimitris Papastamos
Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32
2018-06-21Merge pull request #1392 from dp-arm/dp/cve_2018_3639Dimitris Papastamos
Implement workaround for CVE-2018-3639 on Cortex A57/A72/A73 and A75 Conflicts: services/arm_arch_svc/arm_arch_svc_setup.c
2018-06-20imx8qxp: support SC_R_IRQSTR_SCU2 OFF in system suspendAnson Huang
SC_R_IRQSTR_SCU2 can be OFF in system suspend if there is no wakeup irq enabled from non-secure OS partion. Add wakeup source check to decide if turning off SC_R_IRQSTR_SCU2 or NOT when suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20plat: imx: fix smp boot hang issue when GIC is power downBai Ping
When GIC is power down, all the GIC state will be lost. All the redistributor's state need save/resotre. Additionally, the redistributor's restore need to be done after distributor Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-20imx8qxp: turn off DB when linux suspendAnson Huang
DB is NOT necessary for irqsteer on i.MX8QXP, it can be OFF when linux suspend. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20imx8qm: support MU power off during suspendAnson Huang
Add MU power off support for suspend, it needs to be re-initialized after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-20imx8qxp: support MU power off during suspendAnson Huang
Add MU power off support for suspend, it needs to be re-initialized after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11plat: imx8mm: mask the non-wakeup irq in low power modeBai Ping
Only enable the wakeup irq when system enter DSM mode. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: use ARRAY_SIZE instead of magic numberBai Ping
use ARRAY_SIZE to get the array size. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: enable DSM mode support on imx8mmBai Ping
enable DSM mode on i.MX8MM. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8m: add a common dram PM code for imx8m socBai Ping
re-design the dram power management code to make it more common for all i.MX8M SOCs. code need to refact and optimize to make more better. Using this common code on i.MX8MM first, for i.MX8MQ, will move to this later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: switch the CKIL clock source to 32K OSCBai Ping
Switch the CKIL clock source to 32K OSC. On i.MX8MM, after SOC PoR, the default clock source for CKIL is from divided 24MHz OSC, as 24MHz OSC will be power down when system enters DSM mdoe. So it is better to use 32K OSC as the default clock source after system bootup. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: enable PU domains' clocks before power upBai Ping
VPU, GPU and PCIE's clock need to be on before power on these power domains. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11MLK-18502-02 plat: imx8mm: keep L2 cache memory power in WAIT modeBai Ping
When system enter deepest cpuilde(WAIT mode), the L2 cache memory can be on for retention to increase the system performance. So the WAIT mode with cluster power down should be defined as rentention power state in PSCI. changing the WAIT_OFF_STATE to WAIT_RET_STATE to make sure the l2 cache memory is not clean & invalidate. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11MLK-18502-01 plat: imx8mm: fix audio fifo underrun issueBai Ping
A53 WAIT mode is specific for OS cpuilde. The MASTER1 & MASTER2 mapping in A53 domain should be clear, otherwise the 'noc2supermix' and 'supermix2noc' ADB400 async port will be power down when A53 enters WAIT mode.If the ADB400 is power down in WAIT mode, all the bus request from supermix to noc wrapper will be blocked. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11imx8qxp: move M4 to OS part at lastPeng Fan
With default configuration, M4 and A35 in one partition, M4 is loaded by ROM. "err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);" M4 core will first be moved to non-secure OS part, then the resource used by M4 will be moved to non-secure OS part later. But before the resource be moved to non-secure OS part, M4 core is still running, so a non-secure M4 core access a secure resource will trigger error in M4 side. First mark M4 core as non-movable, after all other resoures moved to OS part, move M4 to OS part. No need to check whether M4 is created a new partition by SCFW, if a partition already created, the call to mark M4 as non-removable will fail, because it M4 is in its own partition. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11imx8qm: move M4 to OS part at lastPeng Fan
With default configuration, M4 and A35 in one partition, M4 is loaded by ROM. "err = sc_rm_move_all(ipc_handle, secure_part, os_part, true, true);" M4 core will first be moved to non-secure OS part, then the resource used by M4 will be moved to non-secure OS part later. But before the resource be moved to non-secure OS part, M4 core is still running, so a non-secure M4 core access a secure resource will trigger error in M4 side. First mark M4 core as non-movable, after all other resoures moved to OS part, move M4 to OS part. No need to check whether M4 is created a new partition by SCFW, if a partition already created, the call to mark M4 as non-removable will fail, because it M4 is in its own partition. Signed-off-by: Peng Fan <peng.fan@nxp.com>
2018-06-11MLK-18343-3: plat: imx8mm: add CAAM supportSilvano di Ninno
- configure Secure memory partition - allocate all CAAM JR to Linux Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11MLK-18343-2: plat: imx8mm: add support for RDC and CSUSilvano di Ninno
move CSU and RDC driver to common/i.mx8m folder and enable the driver for i.mx8mm Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11MLK-18343-1: plat: imx8mm: add BL32 supportSilvano di Ninno
fix entry point for the OP-TEE Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
2018-06-11plat: imx8mm: enable the wait mode support on imx8mmBai Ping
Enable the WAIT mode support in cpuilde to save power. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8mm: cleanup platform.mkSilvano di Ninno
cleanup XLAT and STACK defines the OCRAM size for ATF is big enough for i.MX 8mm there is no need to move code to OCRAM_S Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Acked-by: Jacky Bai <ping.bai@nxp.com>
2018-06-11imx8mm: add HAB supportYe Li
Similar to imx8mq, the U-boot calls SIP call for HAB interfaces, and trap to ATF to run the HAB. Since HAB codes locates in ROM, and need to access OCRAM, CAAM RAM and DDR to authenticate image. Add these relevant memory region to MMU. Also extend the stack size of each core to avoid stack overflow, and extend the BL31 limit to OCRAM end 0x940000. Signed-off-by: Ye Li <ye.li@nxp.com>
2018-06-11plat: imx8mm: add basic imx8mm supportBai Ping
i.MX8MM is a new soc of the i.MX8M family, this patch add the basic support for i.MX8MM. further code optimization needed. WAIT mode support is currently disabled, will be enabled later. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx8m: move hab file to common dir of imx8mBai Ping
As the i.MX8MM and i.MX8MQ share the same hab file, move it to common/imx8m, make it reusable for all i.MX8M SOCs. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx: Fix the IRQSTR power modes for iMX8QM/QXPNitin Garg
make sure to put IRQSTEER SCU into correct power modes. Signed-off-by: Nitin Garg <nitin.garg@nxp.com>
2018-06-11plat: imx8mq: rename files for imx8mqBai Ping
For the i.MX8 media processor, we have i.MX8MQ and i.MX8MM etc. so rename the file name of imx8m_bl31_setup.c and imx8m_psci.c to imx8mq_xxx to make it more clear that these file is specific to i.MX8MQ. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: freescale: update the license identifier with SPDX short identifierBai Ping
clean up the license identifier with short SPDX short identifier. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11SCR-imx-atf.txt: Moved from meta-fsl-mpu-internal.Ann Thornton
Signed-off-by: Ann Thornton <ann.thornton@nxp.com>
2018-06-11plat: imx8qm: Use MU0 for SCU communicationAnson Huang
Use MU0 to comply with boot image usage of MU, Also power on and pass MU1 for OS/Hypervisor. Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
2018-06-11plat: imx8qxp: Use MU0 for SCu communicationTeo Hall
Use MU0 to comply with boot image usage of MU0 Also power on and pass MU1 for OS/Hypervisor Signed-off-by: Teo Hall <teo.hall@nxp.com>
2018-06-11plat: imx: add gic save/restore for imx8qm/qxpBai Ping
In order to save power when AP side is suspend, the DBLOG need to be put into low power mode. GIC need to be power off to save power. before GIC power off, we need to save the GIC setting, then after resume, we need to restore the gic setting. irqsteer need to be used to wakeup the AP side when wakeup interrupt is pending for AP side. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx: add platfrom gicv3 save/restoreBai Ping
The GICv3 save/restore is necessary when GIC is going to power off. the save/restore is common for all imx8 platform, so make it common for imx8. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx: add scu2 irqstr to sec rsrcBai Ping
The irqstr for scu2 is used for AP wakeup if gic is power off, so this resource need to be added to the sec rsrc. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11plat: imx: update the scfw api to the latest oneBai Ping
The SCFW API is updated based on below commit in SCFW: commit 433c7fb773e3a5853e2744ff1f958bb225cd338a Author: Chuck Cannon <chuck.cannon@nxp.com> Date: Tue Apr 17 16:09:56 2018 -0500 Only default start CPUs for EMUL, SIMU, and test builds. Signed-off-by: Bai Ping <ping.bai@nxp.com>
2018-06-11MLK-17591-2: CSU/RDC Add testing capabilitySilvano di Ninno
this patch adds some configuration to test CSU and RDC feature by default this is disable. to enable it add $(eval $(call add_define,CSU_RDC_TEST)) to the platform.mk file under plat/freescale/imx8mq/include this patch configure - CSU for GPIO5 to be secure only - RDC for Cortex A to be Domain ID 0 - GPIO4 to be rw by domain ID 2 to test, stops boot at uboot and run following command: u-boot=> md 0x3024000 03024000:"Synchronous Abort" handler, esr 0x96000210 ELR: 40257504 LR: 402574c0 x0 : 0000000000000009 x1 : 00000000308600b4 x2 : 00000000fdf28804 x3 : 0000000000000000 x4 : 0000000003024000 x5 : 00000000fdf73ad0 x6 : 0000000000000004 x7 : 000000000000000f x8 : 00000000fc8ff7e0 x9 : 0000000000000000 x10: 00000000fc8ff049 x11: 0000000000000021 x12: 0000000000000008 x13: 00000000ffffffff x14: 00000000fc8ffb1c x15: 00000000fc8ffc40 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000fc907da0 x19: 0000000000000040 x20: 0000000000000004 x21: 0000000003024000 x22: 0000000003024000 x23: 00000000fdf7348d x24: 0000000000000008 x25: 0000000000000009 x26: 0000000000000004 x27: 0000000000000004 x28: 00000000fc8ff928 x29: 00000000fc8ff8a0 Resetting CPU ... resetting ... CPU tried to acces GPIO 5 registers and crashes u-boot=> md 0x30230000 30230000:"Synchronous Abort" handler, esr 0x96000210 ELR: 40257504 LR: 402574c0 x0 : 0000000000000009 x1 : 00000000308600b4 x2 : 00000000fdf28804 x3 : 0000000000000000 x4 : 0000000030230000 x5 : 00000000fdf73ad0 x6 : 0000000000000004 x7 : 000000000000000f x8 : 00000000fc8ff7e0 x9 : 0000000000000000 x10: 00000000fc8ff049 x11: 0000000000000021 x12: 0000000000000008 x13: 00000000ffffffff x14: 00000000fc8ffb1c x15: 00000000fc8ffc40 x16: 0000000000000000 x17: 0000000000000000 x18: 00000000fc907da0 x19: 0000000000000040 x20: 0000000000000004 x21: 0000000030230000 x22: 0000000030230000 x23: 00000000fdf7348d x24: 0000000000000008 x25: 0000000000000009 x26: 0000000000000004 x27: 0000000000000004 x28: 00000000fc8ff928 x29: 00000000fc8ff8a0 Resetting CPU ... resetting ... CPU tried to acces GPIO 4 registers and crashes Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
2018-06-11MLK-17591-1: CSU Fix Slave configurationSilvano di Ninno
there is a bug in the CSL assignment. the CSL(n) and CSL(n+1) configuration were reversed. Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-18 19:51:48 +0000