diff options
Diffstat (limited to 'plat/rockchip/rk3399/drivers/dram/suspend.c')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/suspend.c | 31 |
1 files changed, 26 insertions, 5 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index f408d676..42cbf987 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -34,6 +34,7 @@ #include <dram.h> #include <pmu_regs.h> #include <rk3399_def.h> +#include <secure.h> #include <soc.h> #include <suspend.h> @@ -571,14 +572,15 @@ static __sramfunc void pctl_cfg(uint32_t ch, sram_regcpy(PHY_REG(ch, 768), (uintptr_t)¶ms_phy[768], 38); } -static __sramfunc int dram_switch_to_phy_index1( +static __sramfunc int dram_switch_to_next_index( struct rk3399_sdram_params *sdram_params) { uint32_t ch, ch_count; + uint32_t fn = ((mmio_read_32(CTL_REG(0, 111)) >> 16) + 1) & 0x1; mmio_write_32(CIC_BASE + CIC_CTRL0, (((0x3 << 4) | (1 << 2) | 1) << 16) | - (1 << 4) | (1 << 2) | 1); + (fn << 4) | (1 << 2) | 1); while (!(mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2))) ; @@ -591,7 +593,7 @@ static __sramfunc int dram_switch_to_phy_index1( /* LPDDR4 f2 cann't do training, all training will fail */ for (ch = 0; ch < ch_count; ch++) { mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, - 1 << 8); + fn << 8); /* data_training failed */ if (data_training(ch, sdram_params, PI_FULL_TRAINING)) @@ -609,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask, struct rk3399_sdram_params *sdram_params) { uint32_t count; + uint32_t byte; mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); @@ -640,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, } mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT); + + /* Restore the PHY_RX_CAL_DQS value */ + for (byte = 0; byte < 4; byte++) + mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte), + 0xfff << 16, + sdram_params->rx_cal_dqs[0][byte]); } if (channel_mask & (1 << 1)) { count = 0; @@ -653,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask, } mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT); + + /* Restore the PHY_RX_CAL_DQS value */ + for (byte = 0; byte < 4; byte++) + mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte), + 0xfff << 16, + sdram_params->rx_cal_dqs[1][byte]); } return 0; @@ -665,7 +680,7 @@ void dmc_save(void) uint32_t *params_pi; uint32_t *params_phy; uint32_t refdiv, postdiv2, postdiv1, fbdiv; - uint32_t tmp; + uint32_t tmp, ch, byte; params_ctl = sdram_params->pctl_regs.denali_ctl; params_pi = sdram_params->pi_regs.denali_pi; @@ -705,6 +720,12 @@ void dmc_save(void) sram_regcpy((uintptr_t)¶ms_phy[768], PHY_REG(0, 768), 38); sram_regcpy((uintptr_t)¶ms_phy[896], PHY_REG(0, 896), 63); + for (ch = 0; ch < sdram_params->num_channels; ch++) { + for (byte = 0; byte < 4; byte++) + sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) & + mmio_read_32(PHY_REG(ch, 57 + byte * 128)); + } + /* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */ params_phy[957] &= ~(0x3 << 24); params_phy[957] |= 1 << 24; @@ -754,5 +775,5 @@ retry: dram_all_config(sdram_params); /* Switch to index 1 and prepare for DDR frequency switch. */ - dram_switch_to_phy_index1(sdram_params); + dram_switch_to_next_index(sdram_params); } |