diff options
Diffstat (limited to 'plat/mediatek/mt8173/bl31_plat_setup.c')
| -rw-r--r-- | plat/mediatek/mt8173/bl31_plat_setup.c | 18 |
1 files changed, 14 insertions, 4 deletions
diff --git a/plat/mediatek/mt8173/bl31_plat_setup.c b/plat/mediatek/mt8173/bl31_plat_setup.c index 87837759..749009ea 100644 --- a/plat/mediatek/mt8173/bl31_plat_setup.c +++ b/plat/mediatek/mt8173/bl31_plat_setup.c @@ -50,13 +50,15 @@ unsigned long __COHERENT_RAM_START__; unsigned long __COHERENT_RAM_END__; /* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. + * The next 3 constants identify the extents of the code, RO data region and the + * limit of the BL31 image. These addresses are used by the MMU setup code and + * therefore they must be page-aligned. It is the responsibility of the linker + * script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols + * refer to page-aligned addresses. */ #define BL31_RO_BASE (unsigned long)(&__RO_START__) #define BL31_RO_LIMIT (unsigned long)(&__RO_END__) +#define BL31_END (unsigned long)(&__BL31_END__) /* * The next 2 constants identify the extents of the coherent memory region. @@ -108,6 +110,13 @@ static void platform_setup_cpu(void) MCU_BUS_DCM_EN); } +static void platform_setup_sram(void) +{ + /* protect BL31 memory from non-secure read/write access */ + mmio_write_32(SRAMROM_SEC_ADDR, (uint32_t)(BL31_END + 0x3ff) & 0x3fc00); + mmio_write_32(SRAMROM_SEC_CTRL, 0x10000ff9); +} + /******************************************************************************* * Return a pointer to the 'entry_point_info' structure of the next image for * the security state specified. BL33 corresponds to the non-secure image type @@ -156,6 +165,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, void bl31_platform_setup(void) { platform_setup_cpu(); + platform_setup_sram(); plat_delay_timer_init(); |