diff options
Diffstat (limited to 'plat/imx/imx8mq/include/ddrc.h')
| -rw-r--r-- | plat/imx/imx8mq/include/ddrc.h | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/plat/imx/imx8mq/include/ddrc.h b/plat/imx/imx8mq/include/ddrc.h index 8eb42fd8..ed6ebfa1 100644 --- a/plat/imx/imx8mq/include/ddrc.h +++ b/plat/imx/imx8mq/include/ddrc.h @@ -297,6 +297,33 @@ #define DDRC_DFITMG3_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x21b8) #define DDRC_ODTCFG_SHADOW(X) (DDRC_IPS_BASE_ADDR(X) + 0x2240) +#define DRC_PERF_MON_BASE_ADDR(X) 0x3d800000 + (X * 0x2000000) +#define DRC_PERF_MON_CNT0_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x0 +#define DRC_PERF_MON_CNT1_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x4 +#define DRC_PERF_MON_CNT2_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0x8 +#define DRC_PERF_MON_CNT3_CTL(X) DRC_PERF_MON_BASE_ADDR(X) + 0xC +#define DRC_PERF_MON_CNT0_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x20 +#define DRC_PERF_MON_CNT1_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x24 +#define DRC_PERF_MON_CNT2_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x28 +#define DRC_PERF_MON_CNT3_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x2C +#define DRC_PERF_MON_DPCR_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x30 +#define DRC_PERF_MON_MRR0_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x40 +#define DRC_PERF_MON_MRR1_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x44 +#define DRC_PERF_MON_MRR2_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x48 +#define DRC_PERF_MON_MRR3_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x4C +#define DRC_PERF_MON_MRR4_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x50 +#define DRC_PERF_MON_MRR5_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x54 +#define DRC_PERF_MON_MRR6_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x58 +#define DRC_PERF_MON_MRR7_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x5C +#define DRC_PERF_MON_MRR8_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x60 +#define DRC_PERF_MON_MRR9_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x64 +#define DRC_PERF_MON_MRR10_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x68 +#define DRC_PERF_MON_MRR11_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x6C +#define DRC_PERF_MON_MRR12_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x70 +#define DRC_PERF_MON_MRR13_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x74 +#define DRC_PERF_MON_MRR14_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x78 +#define DRC_PERF_MON_MRR15_DAT(X) DRC_PERF_MON_BASE_ADDR(X) + 0x7C + #define IP2APB_DDRPHY_IPS_BASE_ADDR(X) (0x3c000000 + (X * 0x2000000)) #define dwc_ddrphy_apb_rd(addr) mmio_read_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) #define dwc_ddrphy_apb_wr(addr, val) mmio_write_32(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), val) |