diff options
Diffstat (limited to 'plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c')
| -rw-r--r-- | plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c index eaa4492a..b32c81c0 100644 --- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c +++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c @@ -84,7 +84,6 @@ static const struct imx_csu_cfg csu_cfg[] = { {0} }; - static entry_point_info_t bl32_image_ep_info; static entry_point_info_t bl33_image_ep_info; @@ -105,7 +104,7 @@ static uint32_t get_spsr_for_bl33_entry(void) return spsr; } -void bl31_tzc380_setup(void) +static void bl31_tzc380_setup(void) { unsigned int val; @@ -122,7 +121,7 @@ void bl31_tzc380_setup(void) /* Enable 1G-5G S/NS RW */ tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) | - TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); + TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL); } void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1, @@ -196,7 +195,6 @@ void bl31_plat_arch_setup(void) (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE), MT_DEVICE | MT_RW | MT_SECURE); #endif - // Map TEE memory mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW); |