diff options
Diffstat (limited to 'plat/imx/imx8m/gpc_common.c')
| -rw-r--r-- | plat/imx/imx8m/gpc_common.c | 24 |
1 files changed, 14 insertions, 10 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 091cf451..9dc1ec80 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -24,6 +24,8 @@ static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, }; DEFINE_BAKERY_LOCK(gpc_lock); +struct plat_gic_ctx imx_gicv3_ctx; + #pragma weak imx_set_cpu_pwr_off #pragma weak imx_set_cpu_pwr_on #pragma weak imx_set_cpu_lpm @@ -211,15 +213,20 @@ void imx_set_sys_wakeup(unsigned int last_core, bool pdn) } } -#pragma weak imx_noc_slot_config -/* - * this function only need to be override by platform - * that support noc power down, for example: imx8mm. - * otherwize, keep it empty. - */ void imx_noc_slot_config(bool pdn) { - + if (pdn) { + mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(1), NOC_PDN_SLT_CTRL); + mmio_setbits_32(IMX_GPC_BASE + SLTx_CFG(2), NOC_PUP_SLT_CTRL); + /* clear a53's PDN ack, use NOC's PDN ack */ + mmio_clrsetbits_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, 0xffff, NOC_PGC_PDN_ACK); + mmio_setbits_32(IMX_GPC_BASE + NOC_PGC_PCR, 0x1); + } else { + mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(1), NOC_PDN_SLT_CTRL); + mmio_clrbits_32(IMX_GPC_BASE + SLTx_CFG(2), NOC_PUP_SLT_CTRL); + mmio_write_32(IMX_GPC_BASE + PGC_ACK_SEL_A53, A53_DUMMY_PUP_ACK | A53_DUMMY_PDN_ACK); + mmio_clrbits_32(IMX_GPC_BASE + NOC_PGC_PCR, 0x1); + } } /* this is common for all imx8m soc */ @@ -237,9 +244,6 @@ void imx_set_sys_lpm(unsigned int last_core, bool retention) mmio_write_32(IMX_GPC_BASE + SLPCR, val); - /* config the noc power down */ - imx_noc_slot_config(retention); - /* config wakeup irqs' mask in gpc */ imx_set_sys_wakeup(last_core, retention); } |