diff options
Diffstat (limited to 'plat/imx/imx8m/ddr/dram_retention.c')
| -rw-r--r-- | plat/imx/imx8m/ddr/dram_retention.c | 25 |
1 files changed, 8 insertions, 17 deletions
diff --git a/plat/imx/imx8m/ddr/dram_retention.c b/plat/imx/imx8m/ddr/dram_retention.c index 2eb1438a..b46d4410 100644 --- a/plat/imx/imx8m/ddr/dram_retention.c +++ b/plat/imx/imx8m/ddr/dram_retention.c @@ -8,14 +8,12 @@ #include <lib/mmio.h> #include <dram.h> +#include <gpc_reg.h> #include <platform_def.h> #define SRC_DDR1_RCR (IMX_SRC_BASE + 0x1000) #define SRC_DDR2_RCR (IMX_SRC_BASE + 0x1004) -#define PU_PGC_UP_TRG 0xf8 -#define PU_PGC_DN_TRG 0x104 -#define GPC_PU_PWRHSK (IMX_GPC_BASE + 0x01FC) #define CCM_SRC_CTRL_OFFSET (IMX_CCM_BASE + 0x800) #define CCM_CCGR_OFFSET (IMX_CCM_BASE + 0x4000) #define CCM_SRC_CTRL(n) (CCM_SRC_CTRL_OFFSET + 0x10 * (n)) @@ -65,19 +63,12 @@ void dram_enter_retention(void) INFO("PhyInLP3 = 1\n"); dwc_ddrphy_apb_wr(0xd0000, 0x1); -#if defined(PLAT_imx8mq) - /* pwrdnreqn_async adbm/adbs of ddr */ - mmio_clrbits_32(GPC_PU_PWRHSK, BIT(1)); - while (mmio_read_32(GPC_PU_PWRHSK) & BIT(18)) - ; - mmio_setbits_32(GPC_PU_PWRHSK, BIT(1)); -#else /* pwrdnreqn_async adbm/adbs of ddr */ - mmio_clrbits_32(GPC_PU_PWRHSK, BIT(2)); - while (mmio_read_32(GPC_PU_PWRHSK) & BIT(20)) + mmio_clrbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); + while (mmio_read_32(IMX_GPC_BASE + GPC_PU_PWRHSK) & DDRMIX_ADB400_ACK) ; - mmio_setbits_32(GPC_PU_PWRHSK, BIT(2)); -#endif + mmio_setbits_32(IMX_GPC_BASE + GPC_PU_PWRHSK, DDRMIX_ADB400_SYNC); + /* remove PowerOk */ mmio_write_32(SRC_DDR1_RCR, 0x8F000008); @@ -85,8 +76,8 @@ void dram_enter_retention(void) mmio_write_32(CCM_SRC_CTRL(15), 2); /* enable the phy iso */ - mmio_setbits_32(IMX_GPC_BASE + 0xd40, 1); - mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, BIT(5)); + mmio_setbits_32(IMX_GPC_BASE + DDRMIX_PGC, 1); + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_DN_TRG, DDRMIX_PWR_REQ); VERBOSE("dram enter retention\n"); } @@ -107,7 +98,7 @@ void dram_exit_retention(void) mmio_write_32(CCM_SRC_CTRL(15), 2); /* disable iso */ - mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, BIT(5)); + mmio_setbits_32(IMX_GPC_BASE + PU_PGC_UP_TRG, DDRMIX_PWR_REQ); mmio_write_32(SRC_DDR1_RCR, 0x8F000006); /* wait dram pll locked */ |