diff options
Diffstat (limited to 'plat/freescale/common/include/sci/svc/pm/api.h')
| -rwxr-xr-x[-rw-r--r--] | plat/freescale/common/include/sci/svc/pm/api.h | 160 |
1 files changed, 97 insertions, 63 deletions
diff --git a/plat/freescale/common/include/sci/svc/pm/api.h b/plat/freescale/common/include/sci/svc/pm/api.h index d6751289..2d88b7c7 100644..100755 --- a/plat/freescale/common/include/sci/svc/pm/api.h +++ b/plat/freescale/common/include/sci/svc/pm/api.h @@ -31,10 +31,10 @@ * @name Defines for type widths */ /*@{*/ -#define SC_PM_POWER_MODE_W 2 /*!< Width of sc_pm_power_mode_t */ -#define SC_PM_CLOCK_MODE_W 3 /*!< Width of sc_pm_clock_mode_t */ -#define SC_PM_RESET_TYPE_W 1 /*!< Width of sc_pm_reset_type_t */ -#define SC_PM_RESET_REASON_W 3 /*!< Width of sc_pm_reset_reason_t */ +#define SC_PM_POWER_MODE_W 2 /* Width of sc_pm_power_mode_t */ +#define SC_PM_CLOCK_MODE_W 3 /* Width of sc_pm_clock_mode_t */ +#define SC_PM_RESET_TYPE_W 2 /* Width of sc_pm_reset_type_t */ +#define SC_PM_RESET_REASON_W 3 /* Width of sc_pm_reset_reason_t */ /*@}*/ /*! @@ -47,7 +47,82 @@ * @name Defines for ALL parameters */ /*@{*/ -#define SC_PM_CLK_ALL UINT8_MAX /*!< All clocks */ +#define SC_PM_CLK_ALL UINT8_MAX /* All clocks */ +/*@}*/ + +/*! + * @name Defines for sc_pm_power_mode_t + */ +/*@{*/ +#define SC_PM_PW_MODE_OFF 0 /* Power off */ +#define SC_PM_PW_MODE_STBY 1 /* Power in standby */ +#define SC_PM_PW_MODE_LP 2 /* Power in low-power */ +#define SC_PM_PW_MODE_ON 3 /* Power on */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_t + */ +/*@{*/ +#define SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ +#define SC_PM_CLK_MST_BUS 1 /* Master bus clock */ +#define SC_PM_CLK_PER 2 /* Peripheral clock */ +#define SC_PM_CLK_PHY 3 /* Phy clock */ +#define SC_PM_CLK_MISC 4 /* Misc clock */ +#define SC_PM_CLK_MISC0 0 /* Misc 0 clock */ +#define SC_PM_CLK_MISC1 1 /* Misc 1 clock */ +#define SC_PM_CLK_MISC2 2 /* Misc 2 clock */ +#define SC_PM_CLK_MISC3 3 /* Misc 3 clock */ +#define SC_PM_CLK_MISC4 4 /* Misc 4 clock */ +#define SC_PM_CLK_CPU 2 /* CPU clock */ +#define SC_PM_CLK_PLL 4 /* PLL */ +#define SC_PM_CLK_BYPASS 4 /* Bypass clock */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_mode_t + */ +/*@{*/ +#define SC_PM_CLK_MODE_ROM_INIT 0 /* Clock is initialized by ROM. */ +#define SC_PM_CLK_MODE_OFF 1 /* Clock is disabled */ +#define SC_PM_CLK_MODE_ON 2 /* Clock is enabled. */ +#define SC_PM_CLK_MODE_AUTOGATE_SW 3 /* Clock is in SW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_HW 4 /* Clock is in HW autogate mode */ +#define SC_PM_CLK_MODE_AUTOGATE_SW_HW 5 /* Clock is in SW-HW autogate mode */ +/*@}*/ + +/*! + * @name Defines for sc_pm_clk_parent_t + */ +/*@{*/ +#define SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */ +#define SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */ +#define SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */ +#define SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */ +#define SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_type_t + */ +/*@{*/ +#define SC_PM_RESET_TYPE_COLD 0 /* Cold reset */ +#define SC_PM_RESET_TYPE_WARM 1 /* Warm reset */ +#define SC_PM_RESET_TYPE_BOARD 2 /* Board reset */ +/*@}*/ + +/*! + * @name Defines for sc_pm_reset_reason_t + */ +/*@{*/ +#define SC_PM_RESET_REASON_POR 0 /* Power on reset */ +#define SC_PM_RESET_REASON_WARM 1 /* Warm reset */ +#define SC_PM_RESET_REASON_SW 2 /* Software reset */ +#define SC_PM_RESET_REASON_WDOG 3 /* Watchdog reset */ +#define SC_PM_RESET_REASON_LOCKUP 4 /* Lockup reset */ +#define SC_PM_RESET_REASON_TAMPER 5 /* Tamper reset */ +#define SC_PM_RESET_REASON_TEMP 6 /* Temp reset */ +#define SC_PM_RESET_REASON_LOW_VOLT 7 /* Low voltage reset */ /*@}*/ /* Types */ @@ -57,58 +132,22 @@ * SC_PM_PW_MODE_OFF and SC_PM_PW_MODE_ON. The other modes are used only * as system power modes. */ -typedef enum sc_pm_power_mode_e -{ - SC_PM_PW_MODE_OFF = 0, /*!< Power off */ - SC_PM_PW_MODE_STBY = 1, /*!< Power in standby */ - SC_PM_PW_MODE_LP = 2, /*!< Power in low-power */ - SC_PM_PW_MODE_ON = 3 /*!< Power on */ -} sc_pm_power_mode_t; +typedef uint8_t sc_pm_power_mode_t; /*! * This type is used to declare a clock. */ -typedef enum sc_pm_clk_e -{ - SC_PM_CLK_SLV_BUS = 0, /*!< Slave bus clock */ - SC_PM_CLK_MST_BUS = 1, /*!< Master bus clock */ - SC_PM_CLK_PER = 2, /*!< Peripheral clock */ - SC_PM_CLK_PHY = 3, /*!< Phy clock */ - SC_PM_CLK_MISC = 4, /*!< Misc clock */ - SC_PM_CLK_MISC0 = 0, /*!< Misc 0 clock */ - SC_PM_CLK_MISC1 = 1, /*!< Misc 1 clock */ - SC_PM_CLK_MISC2 = 2, /*!< Misc 2 clock */ - SC_PM_CLK_MISC3 = 3, /*!< Misc 3 clock */ - SC_PM_CLK_MISC4 = 4, /*!< Misc 4 clock */ - SC_PM_CLK_CPU = 2, /*!< CPU clock */ - SC_PM_CLK_PLL = 4, /*!< PLL */ - SC_PM_CLK_BYPASS = 4 /*!< Bypass clock */ -} sc_pm_clk_t; +typedef uint8_t sc_pm_clk_t; /*! * This type is used to declare a clock mode. */ -typedef enum sc_pm_clk_mode_e -{ - SC_PM_CLK_MODE_ROM_INIT = 0, /*!< Clock is initialized by ROM. */ - SC_PM_CLK_MODE_OFF = 1, /*!< Clock is disabled */ - SC_PM_CLK_MODE_ON = 2, /*!< Clock is enabled. */ - SC_PM_CLK_MODE_AUTOGATE_SW = 3, /*!< Clock is in SW autogate mode */ - SC_PM_CLK_MODE_AUTOGATE_HW = 4, /*!< Clock is in HW autogate mode */ - SC_PM_CLK_MODE_AUTOGATE_SW_HW = 5, /*!< Clock is in SW-HW autogate mode */ -} sc_pm_clk_mode_t; +typedef uint8_t sc_pm_clk_mode_t; /*! * This type is used to declare the clock parent. */ -typedef enum sc_pm_clk_parent_e -{ - XTAL = 0, /*! < Parent is XTAL. */ - PLL0 = 1, /*! < Parent is PLL0 */ - PLL1 = 2, /*! < Parent is PLL1 or PLL0/2 */ - PLL2 = 3, /*! < Parent in PLL2 or PLL0/4 */ - BYPS = 4 /*! < Parent is a bypass clock. */ -} sc_pm_clk_parent_t; +typedef uint8_t sc_pm_clk_parent_t; /*! * This type is used to declare clock rates. @@ -118,26 +157,12 @@ typedef uint32_t sc_pm_clock_rate_t; /*! * This type is used to declare a desired reset type. */ -typedef enum sc_pm_reset_type_e -{ - SC_PM_RESET_TYPE_COLD = 0, /*!< Cold reset */ - SC_PM_RESET_TYPE_WARM = 1 /*!< Warm reset */ -} sc_pm_reset_type_t; +typedef uint8_t sc_pm_reset_type_t; /*! * This type is used to declare a reason for a reset. */ -typedef enum sc_pm_reset_reason_e -{ - SC_PM_RESET_REASON_POR = 0, /*!< Power on reset */ - SC_PM_RESET_REASON_WARM = 1, /*!< Warm reset */ - SC_PM_RESET_REASON_SW = 2, /*!< Software reset */ - SC_PM_RESET_REASON_WDOG = 3, /*!< Watchdog reset */ - SC_PM_RESET_REASON_LOCKUP = 4, /*!< Lockup reset */ - SC_PM_RESET_REASON_TAMPER = 5, /*!< Tamper reset */ - SC_PM_RESET_REASON_TEMP = 6, /*!< Temp reset */ - SC_PM_RESET_REASON_LOW_VOLT = 7, /*!< Low voltage reset */ -} sc_pm_reset_reason_t; +typedef uint8_t sc_pm_reset_reason_t; /* Functions */ @@ -201,6 +226,11 @@ sc_err_t sc_pm_get_sys_power_mode(sc_ipc_t ipc, sc_rm_pt_t pt, * will return an error. Resources set to SC_PM_PW_MODE_ON will reflect the * power mode of the partition and will change as that changes. * + * Note some resources are still not accessible even when powered up if bus + * transactions go through a fabric not powered up. Examples of this are + * resources in display and capture subsystems which require the display + * controller or the imaging subsytem to be powered up first. + * * @see sc_pm_set_sys_power_mode(). */ sc_err_t sc_pm_set_resource_power_mode(sc_ipc_t ipc, sc_rsrc_t resource, @@ -293,7 +323,6 @@ sc_err_t sc_pm_get_clock_rate(sc_ipc_t ipc, sc_rsrc_t resource, sc_err_t sc_pm_clock_enable(sc_ipc_t ipc, sc_rsrc_t resource, sc_pm_clk_t clk, bool enable, bool autog); - /*! * This function sets the parent of a resource's clock. * This function should only be called when the clock is disabled. @@ -367,6 +396,8 @@ sc_err_t sc_pm_reset(sc_ipc_t ipc, sc_pm_reset_type_t type); * * @param[in] ipc IPC handle * @param[out] reason pointer to return reset reason + * + * @return Returns an error code (SC_ERR_NONE = success). */ sc_err_t sc_pm_reset_reason(sc_ipc_t ipc, sc_pm_reset_reason_t *reason); @@ -407,6 +438,8 @@ sc_err_t sc_pm_boot(sc_ipc_t ipc, sc_rm_pt_t pt, * of the booting CPU must be able to handle peripherals and SC state that * that are not reset. * + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * * If this function returns, then the reset did not occur due to an * invalid parameter. */ @@ -429,6 +462,8 @@ void sc_pm_reboot(sc_ipc_t ipc, sc_pm_reset_type_t type); * of the booting CPU must be able to handle peripherals and SC state that * that are not reset. * + * If \a type is SC_PM_RESET_TYPE_BOARD, then return with no action. + * * @return Returns an error code (SC_ERR_NONE = success). * * Return errors: @@ -466,4 +501,3 @@ sc_err_t sc_pm_cpu_start(sc_ipc_t ipc, sc_rsrc_t resource, bool enable, #endif /* _SC_PM_API_H */ /**@}*/ - |