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-rw-r--r--lib/cpus/aarch64/neoverse_zeus.S12
-rw-r--r--lib/el3_runtime/aarch64/context.S21
-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c29
-rw-r--r--lib/libc/assert.c9
-rw-r--r--lib/psci/psci_common.c17
-rw-r--r--lib/psci/psci_private.h19
6 files changed, 77 insertions, 30 deletions
diff --git a/lib/cpus/aarch64/neoverse_zeus.S b/lib/cpus/aarch64/neoverse_zeus.S
index 3d850137..44882b45 100644
--- a/lib/cpus/aarch64/neoverse_zeus.S
+++ b/lib/cpus/aarch64/neoverse_zeus.S
@@ -46,6 +46,16 @@ func neoverse_zeus_errata_report
endfunc neoverse_zeus_errata_report
#endif
+func neoverse_zeus_reset_func
+ mov x19, x30
+
+ /* Disable speculative loads */
+ msr SSBS, xzr
+
+ isb
+ ret x19
+endfunc neoverse_zeus_reset_func
+
/* ---------------------------------------------
* This function provides Neoverse-Zeus specific
* register information for crash reporting.
@@ -66,5 +76,5 @@ func neoverse_zeus_cpu_reg_dump
endfunc neoverse_zeus_cpu_reg_dump
declare_cpu_ops neoverse_zeus, NEOVERSE_ZEUS_MIDR, \
- CPU_NO_RESET_FUNC, \
+ neoverse_zeus_reset_func, \
neoverse_zeus_core_pwr_dwn
diff --git a/lib/el3_runtime/aarch64/context.S b/lib/el3_runtime/aarch64/context.S
index 53dc02e6..37bb12c8 100644
--- a/lib/el3_runtime/aarch64/context.S
+++ b/lib/el3_runtime/aarch64/context.S
@@ -145,6 +145,17 @@ func el1_sysregs_context_save
str x14, [x0, #CTX_CNTKCTL_EL1]
#endif
+ /* Save MTE system registers if the build has instructed so */
+#if CTX_INCLUDE_MTE_REGS
+ mrs x15, TFSRE0_EL1
+ mrs x16, TFSR_EL1
+ stp x15, x16, [x0, #CTX_TFSRE0_EL1]
+
+ mrs x9, RGSR_EL1
+ mrs x10, GCR_EL1
+ stp x9, x10, [x0, #CTX_RGSR_EL1]
+#endif
+
ret
endfunc el1_sysregs_context_save
@@ -229,6 +240,16 @@ func el1_sysregs_context_restore
ldr x14, [x0, #CTX_CNTKCTL_EL1]
msr cntkctl_el1, x14
#endif
+ /* Restore MTE system registers if the build has instructed so */
+#if CTX_INCLUDE_MTE_REGS
+ ldp x11, x12, [x0, #CTX_TFSRE0_EL1]
+ msr TFSRE0_EL1, x11
+ msr TFSR_EL1, x12
+
+ ldp x13, x14, [x0, #CTX_RGSR_EL1]
+ msr RGSR_EL1, x13
+ msr GCR_EL1, x14
+#endif
/* No explict ISB required here as ERET covers it */
ret
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index bd5b3aa6..446d9da9 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -137,17 +137,30 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
#endif /* !CTX_INCLUDE_PAUTH_REGS */
- unsigned int mte = get_armv8_5_mte_support();
-
/*
- * Enable MTE support unilaterally for normal world if the CPU supports
- * it.
+ * Enable MTE support. Support is enabled unilaterally for the normal
+ * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
+ * set.
*/
- if (mte != MTE_UNIMPLEMENTED) {
- if (security_state == NON_SECURE) {
- scr_el3 |= SCR_ATA_BIT;
- }
+ unsigned int mte = get_armv8_5_mte_support();
+#if CTX_INCLUDE_MTE_REGS
+ assert(mte == MTE_IMPLEMENTED_ELX);
+ scr_el3 |= SCR_ATA_BIT;
+#else
+ if (mte == MTE_IMPLEMENTED_EL0) {
+ /*
+ * Can enable MTE across both worlds as no MTE registers are
+ * used
+ */
+ scr_el3 |= SCR_ATA_BIT;
+ } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
+ /*
+ * Can only enable MTE in Non-Secure world without register
+ * saving
+ */
+ scr_el3 |= SCR_ATA_BIT;
}
+#endif
#ifdef IMAGE_BL31
/*
diff --git a/lib/libc/assert.c b/lib/libc/assert.c
index 60f1a866..49f59db1 100644
--- a/lib/libc/assert.c
+++ b/lib/libc/assert.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,7 +18,8 @@
*/
#if PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_VERBOSE
-void __assert(const char *file, unsigned int line, const char *assertion)
+void __dead2 __assert(const char *file, unsigned int line,
+ const char *assertion)
{
printf("ASSERT: %s:%d:%s\n", file, line, assertion);
backtrace("assert");
@@ -26,7 +27,7 @@ void __assert(const char *file, unsigned int line, const char *assertion)
plat_panic_handler();
}
#elif PLAT_LOG_LEVEL_ASSERT >= LOG_LEVEL_INFO
-void __assert(const char *file, unsigned int line)
+void __dead2 __assert(const char *file, unsigned int line)
{
printf("ASSERT: %s:%d\n", file, line);
backtrace("assert");
@@ -34,7 +35,7 @@ void __assert(const char *file, unsigned int line)
plat_panic_handler();
}
#else
-void __assert(void)
+void __dead2 __assert(void)
{
backtrace("assert");
(void)console_flush();
diff --git a/lib/psci/psci_common.c b/lib/psci/psci_common.c
index 55a0d872..7c42be7e 100644
--- a/lib/psci/psci_common.c
+++ b/lib/psci/psci_common.c
@@ -159,9 +159,10 @@ void psci_query_sys_suspend_pwrstate(psci_power_state_t *state_info)
******************************************************************************/
unsigned int psci_is_last_on_cpu(void)
{
- int cpu_idx, my_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx, my_idx = plat_my_core_pos();
- for (cpu_idx = 0; cpu_idx < PLATFORM_CORE_COUNT; cpu_idx++) {
+ for (cpu_idx = 0; cpu_idx < (unsigned int)PLATFORM_CORE_COUNT;
+ cpu_idx++) {
if (cpu_idx == my_idx) {
assert(psci_get_aff_info_state() == AFF_STATE_ON);
continue;
@@ -207,7 +208,7 @@ static void psci_set_req_local_pwr_state(unsigned int pwrlvl,
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < PLATFORM_CORE_COUNT)) {
+ (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx] = req_pwr_state;
}
}
@@ -238,12 +239,12 @@ void __init psci_init_req_local_pwr_states(void)
* assertion is added to prevent us from accessing the CPU power level.
*****************************************************************************/
static plat_local_state_t *psci_get_req_local_pwr_states(unsigned int pwrlvl,
- int cpu_idx)
+ unsigned int cpu_idx)
{
assert(pwrlvl > PSCI_CPU_PWR_LVL);
if ((pwrlvl > PSCI_CPU_PWR_LVL) && (pwrlvl <= PLAT_MAX_PWR_LVL) &&
- (cpu_idx < PLATFORM_CORE_COUNT)) {
+ (cpu_idx < (unsigned int) PLATFORM_CORE_COUNT)) {
return &psci_req_local_pwr_states[pwrlvl - 1U][cpu_idx];
} else
return NULL;
@@ -352,7 +353,7 @@ static void psci_set_target_local_pwr_states(unsigned int end_pwrlvl,
/*******************************************************************************
* PSCI helper function to get the parent nodes corresponding to a cpu_index.
******************************************************************************/
-void psci_get_parent_pwr_domain_nodes(int cpu_idx,
+void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
unsigned int end_lvl,
unsigned int *node_index)
{
@@ -418,7 +419,7 @@ void psci_do_state_coordination(unsigned int end_pwrlvl,
psci_power_state_t *state_info)
{
unsigned int lvl, parent_idx, cpu_idx = plat_my_core_pos();
- int start_idx;
+ unsigned int start_idx;
unsigned int ncpus;
plat_local_state_t target_state, *req_states;
@@ -764,7 +765,7 @@ int psci_validate_entry_point(entry_point_info_t *ep,
void psci_warmboot_entrypoint(void)
{
unsigned int end_pwrlvl;
- int cpu_idx = (int) plat_my_core_pos();
+ unsigned int cpu_idx = plat_my_core_pos();
unsigned int parent_nodes[PLAT_MAX_PWR_LVL] = {0};
psci_power_state_t state_info = { {PSCI_LOCAL_STATE_RUN} };
diff --git a/lib/psci/psci_private.h b/lib/psci/psci_private.h
index bbcc5cfe..b49847c9 100644
--- a/lib/psci/psci_private.h
+++ b/lib/psci/psci_private.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -55,16 +55,16 @@ static inline aff_info_state_t psci_get_aff_info_state(void)
return get_cpu_data(psci_svc_cpu_data.aff_info_state);
}
-static inline aff_info_state_t psci_get_aff_info_state_by_idx(int idx)
+static inline aff_info_state_t psci_get_aff_info_state_by_idx(unsigned int idx)
{
- return get_cpu_data_by_index((unsigned int)idx,
+ return get_cpu_data_by_index(idx,
psci_svc_cpu_data.aff_info_state);
}
-static inline void psci_set_aff_info_state_by_idx(int idx,
+static inline void psci_set_aff_info_state_by_idx(unsigned int idx,
aff_info_state_t aff_state)
{
- set_cpu_data_by_index((unsigned int)idx,
+ set_cpu_data_by_index(idx,
psci_svc_cpu_data.aff_info_state, aff_state);
}
@@ -88,9 +88,10 @@ static inline plat_local_state_t psci_get_cpu_local_state(void)
return get_cpu_data(psci_svc_cpu_data.local_state);
}
-static inline plat_local_state_t psci_get_cpu_local_state_by_idx(int idx)
+static inline plat_local_state_t psci_get_cpu_local_state_by_idx(
+ unsigned int idx)
{
- return get_cpu_data_by_index((unsigned int)idx,
+ return get_cpu_data_by_index(idx,
psci_svc_cpu_data.local_state);
}
@@ -113,7 +114,7 @@ typedef struct non_cpu_pwr_domain_node {
* Index of the first CPU power domain node level 0 which has this node
* as its parent.
*/
- int cpu_start_idx;
+ unsigned int cpu_start_idx;
/*
* Number of CPU power domains which are siblings of the domain indexed
@@ -269,7 +270,7 @@ void psci_get_target_local_pwr_states(unsigned int end_pwrlvl,
psci_power_state_t *target_state);
int psci_validate_entry_point(entry_point_info_t *ep,
uintptr_t entrypoint, u_register_t context_id);
-void psci_get_parent_pwr_domain_nodes(int cpu_idx,
+void psci_get_parent_pwr_domain_nodes(unsigned int cpu_idx,
unsigned int end_lvl,
unsigned int *node_index);
void psci_do_state_coordination(unsigned int end_pwrlvl,
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-23 22:10:07 +0000