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-rw-r--r--lib/el3_runtime/aarch64/context_mgmt.c4
-rw-r--r--lib/psci/psci_on.c10
2 files changed, 11 insertions, 3 deletions
diff --git a/lib/el3_runtime/aarch64/context_mgmt.c b/lib/el3_runtime/aarch64/context_mgmt.c
index a05ee5a6..d65e02d5 100644
--- a/lib/el3_runtime/aarch64/context_mgmt.c
+++ b/lib/el3_runtime/aarch64/context_mgmt.c
@@ -142,11 +142,11 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
* world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
* set.
*/
- unsigned int mte = get_armv8_5_mte_support();
#if CTX_INCLUDE_MTE_REGS
- assert(mte == MTE_IMPLEMENTED_ELX);
+ assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
scr_el3 |= SCR_ATA_BIT;
#else
+ unsigned int mte = get_armv8_5_mte_support();
if (mte == MTE_IMPLEMENTED_EL0) {
/*
* Can enable MTE across both worlds as no MTE registers are
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index aa6b324e..470b4f33 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -182,6 +182,14 @@ void psci_cpu_on_finish(int cpu_idx, const psci_power_state_t *state_info)
#endif
/*
+ * Plat. management: Perform any platform specific actions which
+ * can only be done with the cpu and the cluster guaranteed to
+ * be coherent.
+ */
+ if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL)
+ psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
+
+ /*
* All the platform specific actions for turning this cpu
* on have completed. Perform enough arch.initialization
* to run in the non-secure address space.