diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/arch/aarch32/el3_common_macros.S | 2 | ||||
| -rw-r--r-- | include/arch/aarch64/el3_common_macros.S | 2 | ||||
| -rw-r--r-- | include/drivers/delay_timer.h | 25 | ||||
| -rw-r--r-- | include/drivers/st/stm32_hash.h | 2 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a65.h | 31 | ||||
| -rw-r--r-- | include/lib/cpus/aarch64/cortex_a65ae.h | 31 |
6 files changed, 89 insertions, 4 deletions
diff --git a/include/arch/aarch32/el3_common_macros.S b/include/arch/aarch32/el3_common_macros.S index c62d7d77..7559de44 100644 --- a/include/arch/aarch32/el3_common_macros.S +++ b/include/arch/aarch32/el3_common_macros.S @@ -339,7 +339,7 @@ bl zeromem #endif -#ifdef IMAGE_BL1 +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) /* ----------------------------------------------------- * Copy data from ROM to RAM. * ----------------------------------------------------- diff --git a/include/arch/aarch64/el3_common_macros.S b/include/arch/aarch64/el3_common_macros.S index 53396d44..ee20d5b2 100644 --- a/include/arch/aarch64/el3_common_macros.S +++ b/include/arch/aarch64/el3_common_macros.S @@ -366,7 +366,7 @@ bl zeromem #endif -#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_IN_XIP_MEM) +#if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM) adrp x0, __DATA_RAM_START__ add x0, x0, :lo12:__DATA_RAM_START__ adrp x1, __DATA_ROM_START__ diff --git a/include/drivers/delay_timer.h b/include/drivers/delay_timer.h index 684f1c3c..e5044cc6 100644 --- a/include/drivers/delay_timer.h +++ b/include/drivers/delay_timer.h @@ -1,5 +1,6 @@ /* - * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2019, Linaro Limited * * SPDX-License-Identifier: BSD-3-Clause */ @@ -7,8 +8,11 @@ #ifndef DELAY_TIMER_H #define DELAY_TIMER_H +#include <stdbool.h> #include <stdint.h> +#include <arch_helpers.h> + /******************************************************************** * A simple timer driver providing synchronous delay functionality. * The driver must be initialized with a structure that provides a @@ -23,6 +27,25 @@ typedef struct timer_ops { uint32_t clk_div; } timer_ops_t; +static inline uint64_t timeout_cnt_us2cnt(uint32_t us) +{ + return ((uint64_t)us * (uint64_t)read_cntfrq_el0()) / 1000000ULL; +} + +static inline uint64_t timeout_init_us(uint32_t us) +{ + uint64_t cnt = timeout_cnt_us2cnt(us); + + cnt += read_cntfrq_el0(); + + return cnt; +} + +static inline bool timeout_elapsed(uint64_t expire_cnt) +{ + return read_cntpct_el0() > expire_cnt; +} + void mdelay(uint32_t msec); void udelay(uint32_t usec); void timer_init(const timer_ops_t *ops_ptr); diff --git a/include/drivers/st/stm32_hash.h b/include/drivers/st/stm32_hash.h index 969d7aa1..df04730d 100644 --- a/include/drivers/st/stm32_hash.h +++ b/include/drivers/st/stm32_hash.h @@ -14,7 +14,7 @@ enum stm32_hash_algo_mode { HASH_SHA256 }; -int stm32_hash_update(const uint8_t *buffer, uint32_t length); +int stm32_hash_update(const uint8_t *buffer, size_t length); int stm32_hash_final(uint8_t *digest); int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length, uint8_t *digest); diff --git a/include/lib/cpus/aarch64/cortex_a65.h b/include/lib/cpus/aarch64/cortex_a65.h new file mode 100644 index 00000000..0df34c9c --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65_H +#define CORTEX_A65_H + +#include <lib/utils_def.h> + +#define CORTEX_A65_MIDR U(0x410FD060) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65_H */ diff --git a/include/lib/cpus/aarch64/cortex_a65ae.h b/include/lib/cpus/aarch64/cortex_a65ae.h new file mode 100644 index 00000000..bd4a881a --- /dev/null +++ b/include/lib/cpus/aarch64/cortex_a65ae.h @@ -0,0 +1,31 @@ +/* + * Copyright (c) 2019, Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CORTEX_A65AE_H +#define CORTEX_A65AE_H + +#include <lib/utils_def.h> + +#define CORTEX_A65AE_MIDR U(0x410FD430) + +/******************************************************************************* + * CPU Extended Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_ECTLR_EL1 S3_0_C15_C1_4 + +/******************************************************************************* + * CPU Auxiliary Control register specific definitions + ******************************************************************************/ +#define CORTEX_A65AE_CPUACTLR_EL1 S3_0_C15_C1_0 + +/******************************************************************************* + * CPU Power Control register specific definitions + ******************************************************************************/ + +#define CORTEX_A65AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7 +#define CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0) + +#endif /* CORTEX_A65AE_H */ |