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-rw-r--r--drivers/amlogic/crypto/sha_dma.c5
-rw-r--r--drivers/arm/gic/v3/gicv3_main.c191
-rw-r--r--drivers/partition/gpt.c5
-rw-r--r--drivers/partition/partition.c14
4 files changed, 148 insertions, 67 deletions
diff --git a/drivers/amlogic/crypto/sha_dma.c b/drivers/amlogic/crypto/sha_dma.c
index d48ded98..fceb1c0d 100644
--- a/drivers/amlogic/crypto/sha_dma.c
+++ b/drivers/amlogic/crypto/sha_dma.c
@@ -9,10 +9,7 @@
#include <crypto/sha_dma.h>
#include <lib/mmio.h>
-#define AML_SHA_DMA_BASE 0xc883e000
-
-#define AML_SHA_DMA_DESC (AML_SHA_DMA_BASE + 0x08)
-#define AML_SHA_DMA_STATUS (AML_SHA_DMA_BASE + 0x18)
+#include "aml_private.h"
#define ASD_MODE_SHA224 0x7
#define ASD_MODE_SHA256 0x6
diff --git a/drivers/arm/gic/v3/gicv3_main.c b/drivers/arm/gic/v3/gicv3_main.c
index 94a20ba0..fb49a579 100644
--- a/drivers/arm/gic/v3/gicv3_main.c
+++ b/drivers/arm/gic/v3/gicv3_main.c
@@ -16,7 +16,6 @@
#include "gicv3_private.h"
const gicv3_driver_data_t *gicv3_driver_data;
-static unsigned int gicv2_compat;
/*
* Spinlock to guard registers needing read-modify-write. APIs protected by this
@@ -60,51 +59,61 @@ static spinlock_t gic_lock;
void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
{
unsigned int gic_version;
+ unsigned int gicv2_compat;
assert(plat_driver_data != NULL);
assert(plat_driver_data->gicd_base != 0U);
- assert(plat_driver_data->gicr_base != 0U);
assert(plat_driver_data->rdistif_num != 0U);
assert(plat_driver_data->rdistif_base_addrs != NULL);
assert(IS_IN_EL3());
- assert(plat_driver_data->interrupt_props_num > 0 ?
- plat_driver_data->interrupt_props != NULL : 1);
+ assert((plat_driver_data->interrupt_props_num != 0U) ?
+ (plat_driver_data->interrupt_props != NULL) : 1);
/* Check for system register support */
-#ifdef __aarch64__
+#ifndef __aarch64__
+ assert((read_id_pfr1() &
+ (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
+#else
assert((read_id_aa64pfr0_el1() &
(ID_AA64PFR0_GIC_MASK << ID_AA64PFR0_GIC_SHIFT)) != 0U);
-#else
- assert((read_id_pfr1() & (ID_PFR1_GIC_MASK << ID_PFR1_GIC_SHIFT)) != 0U);
-#endif /* __aarch64__ */
+#endif /* !__aarch64__ */
/* The GIC version should be 3.0 */
gic_version = gicd_read_pidr2(plat_driver_data->gicd_base);
- gic_version >>= PIDR2_ARCH_REV_SHIFT;
+ gic_version >>= PIDR2_ARCH_REV_SHIFT;
gic_version &= PIDR2_ARCH_REV_MASK;
assert(gic_version == ARCH_REV_GICV3);
/*
- * Find out whether the GIC supports the GICv2 compatibility mode. The
- * ARE_S bit resets to 0 if supported
+ * Find out whether the GIC supports the GICv2 compatibility mode.
+ * The ARE_S bit resets to 0 if supported
*/
gicv2_compat = gicd_read_ctlr(plat_driver_data->gicd_base);
gicv2_compat >>= CTLR_ARE_S_SHIFT;
- gicv2_compat = !(gicv2_compat & CTLR_ARE_S_MASK);
-
- /*
- * Find the base address of each implemented Redistributor interface.
- * The number of interfaces should be equal to the number of CPUs in the
- * system. The memory for saving these addresses has to be allocated by
- * the platform port
- */
- gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
- plat_driver_data->rdistif_num,
- plat_driver_data->gicr_base,
- plat_driver_data->mpidr_to_core_pos);
-
+ gicv2_compat = gicv2_compat & CTLR_ARE_S_MASK;
+
+ if (plat_driver_data->gicr_base != 0U) {
+ /*
+ * Find the base address of each implemented Redistributor interface.
+ * The number of interfaces should be equal to the number of CPUs in the
+ * system. The memory for saving these addresses has to be allocated by
+ * the platform port
+ */
+ gicv3_rdistif_base_addrs_probe(plat_driver_data->rdistif_base_addrs,
+ plat_driver_data->rdistif_num,
+ plat_driver_data->gicr_base,
+ plat_driver_data->mpidr_to_core_pos);
+#if !HW_ASSISTED_COHERENCY
+ /*
+ * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
+ */
+ flush_dcache_range((uintptr_t)(plat_driver_data->rdistif_base_addrs),
+ plat_driver_data->rdistif_num *
+ sizeof(*(plat_driver_data->rdistif_base_addrs)));
+#endif
+ }
gicv3_driver_data = plat_driver_data;
/*
@@ -112,19 +121,19 @@ void __init gicv3_driver_init(const gicv3_driver_data_t *plat_driver_data)
* enabled. When the secondary CPU boots up, it initializes the
* GICC/GICR interface with the caches disabled. Hence flush the
* driver data to ensure coherency. This is not required if the
- * platform has HW_ASSISTED_COHERENCY or WARMBOOT_ENABLE_DCACHE_EARLY
- * enabled.
+ * platform has HW_ASSISTED_COHERENCY enabled.
*/
-#if !(HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY)
- flush_dcache_range((uintptr_t) &gicv3_driver_data,
- sizeof(gicv3_driver_data));
- flush_dcache_range((uintptr_t) gicv3_driver_data,
- sizeof(*gicv3_driver_data));
+#if !HW_ASSISTED_COHERENCY
+ flush_dcache_range((uintptr_t)&gicv3_driver_data,
+ sizeof(gicv3_driver_data));
+ flush_dcache_range((uintptr_t)gicv3_driver_data,
+ sizeof(*gicv3_driver_data));
#endif
- INFO("GICv3 %s legacy support detected."
- " ARM GICV3 driver initialized in EL3\n",
- gicv2_compat ? "with" : "without");
+ INFO("GICv3 with%s legacy support detected."
+ " ARM GICv3 driver initialized in EL3\n",
+ (gicv2_compat == 0U) ? "" : "out");
+
}
/*******************************************************************************
@@ -192,6 +201,7 @@ void gicv3_rdistif_init(unsigned int proc_num)
gicv3_rdistif_on(proc_num);
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ assert(gicr_base != 0U);
/* Set the default attribute of all SGIs and PPIs */
gicv3_ppi_sgi_config_defaults(gicr_base);
@@ -313,6 +323,7 @@ void gicv3_cpuif_disable(unsigned int proc_num)
/* Mark the connected core as asleep */
gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
+ assert(gicr_base != 0U);
gicv3_rdistif_mark_core_asleep(gicr_base);
}
@@ -629,7 +640,9 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
num_ints &= TYPER_IT_LINES_NO_MASK;
num_ints = (num_ints + 1U) << 5;
- assert(num_ints <= (MAX_SPI_ID + 1U));
+ /* Filter out special INTIDs 1020-1023 */
+ if (num_ints > (MAX_SPI_ID + 1U))
+ num_ints = MAX_SPI_ID + 1U;
/* Wait for pending write to complete */
gicd_wait_for_pending_write(gicd_base);
@@ -637,31 +650,31 @@ void gicv3_distif_save(gicv3_dist_ctx_t * const dist_ctx)
/* Save the GICD_CTLR */
dist_ctx->gicd_ctlr = gicd_read_ctlr(gicd_base);
- /* Save GICD_IGROUPR for INTIDs 32 - 1020 */
+ /* Save GICD_IGROUPR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
- /* Save GICD_ISENABLER for INT_IDs 32 - 1020 */
+ /* Save GICD_ISENABLER for INT_IDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
- /* Save GICD_ISPENDR for INTIDs 32 - 1020 */
+ /* Save GICD_ISPENDR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
- /* Save GICD_ISACTIVER for INTIDs 32 - 1020 */
+ /* Save GICD_ISACTIVER for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
- /* Save GICD_IPRIORITYR for INTIDs 32 - 1020 */
+ /* Save GICD_IPRIORITYR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
- /* Save GICD_ICFGR for INTIDs 32 - 1020 */
+ /* Save GICD_ICFGR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
- /* Save GICD_IGRPMODR for INTIDs 32 - 1020 */
+ /* Save GICD_IGRPMODR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
- /* Save GICD_NSACR for INTIDs 32 - 1020 */
+ /* Save GICD_NSACR for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
- /* Save GICD_IROUTER for INTIDs 32 - 1024 */
+ /* Save GICD_IROUTER for INTIDs 32 - 1019 */
SAVE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
/*
@@ -707,24 +720,26 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
num_ints &= TYPER_IT_LINES_NO_MASK;
num_ints = (num_ints + 1U) << 5;
- assert(num_ints <= (MAX_SPI_ID + 1U));
+ /* Filter out special INTIDs 1020-1023 */
+ if (num_ints > (MAX_SPI_ID + 1U))
+ num_ints = MAX_SPI_ID + 1U;
- /* Restore GICD_IGROUPR for INTIDs 32 - 1020 */
+ /* Restore GICD_IGROUPR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igroupr, IGROUPR);
- /* Restore GICD_IPRIORITYR for INTIDs 32 - 1020 */
+ /* Restore GICD_IPRIORITYR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ipriorityr, IPRIORITYR);
- /* Restore GICD_ICFGR for INTIDs 32 - 1020 */
+ /* Restore GICD_ICFGR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, icfgr, ICFGR);
- /* Restore GICD_IGRPMODR for INTIDs 32 - 1020 */
+ /* Restore GICD_IGRPMODR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, igrpmodr, IGRPMODR);
- /* Restore GICD_NSACR for INTIDs 32 - 1020 */
+ /* Restore GICD_NSACR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, nsacr, NSACR);
- /* Restore GICD_IROUTER for INTIDs 32 - 1020 */
+ /* Restore GICD_IROUTER for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, irouter, IROUTER);
/*
@@ -732,13 +747,13 @@ void gicv3_distif_init_restore(const gicv3_dist_ctx_t * const dist_ctx)
* configured.
*/
- /* Restore GICD_ISENABLER for INT_IDs 32 - 1020 */
+ /* Restore GICD_ISENABLER for INT_IDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isenabler, ISENABLER);
- /* Restore GICD_ISPENDR for INTIDs 32 - 1020 */
+ /* Restore GICD_ISPENDR for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, ispendr, ISPENDR);
- /* Restore GICD_ISACTIVER for INTIDs 32 - 1020 */
+ /* Restore GICD_ISACTIVER for INTIDs 32 - 1019 */
RESTORE_GICD_REGS(gicd_base, dist_ctx, num_ints, isactiver, ISACTIVER);
/* Restore the GICD_CTLR */
@@ -1081,3 +1096,71 @@ unsigned int gicv3_set_pmr(unsigned int mask)
return old_mask;
}
+
+/*******************************************************************************
+ * This function delegates the responsibility of discovering the corresponding
+ * Redistributor frames to each CPU itself. It is a modified version of
+ * gicv3_rdistif_base_addrs_probe() and is executed by each CPU in the platform
+ * unlike the previous way in which only the Primary CPU did the discovery of
+ * all the Redistributor frames for every CPU. It also handles the scenario in
+ * which the frames of various CPUs are not contiguous in physical memory.
+ ******************************************************************************/
+int gicv3_rdistif_probe(const uintptr_t gicr_frame)
+{
+ u_register_t mpidr;
+ unsigned int proc_num, proc_self;
+ uint64_t typer_val;
+ uintptr_t rdistif_base;
+ bool gicr_frame_found = false;
+
+ assert(gicv3_driver_data->gicr_base == 0U);
+
+ /* Ensure this function is called with Data Cache enabled */
+#ifndef __aarch64__
+ assert((read_sctlr() & SCTLR_C_BIT) != 0U);
+#else
+ assert((read_sctlr_el3() & SCTLR_C_BIT) != 0U);
+#endif /* !__aarch64__ */
+
+ proc_self = gicv3_driver_data->mpidr_to_core_pos(read_mpidr_el1());
+ rdistif_base = gicr_frame;
+ do {
+ typer_val = gicr_read_typer(rdistif_base);
+ if (gicv3_driver_data->mpidr_to_core_pos != NULL) {
+ mpidr = mpidr_from_gicr_typer(typer_val);
+ proc_num = gicv3_driver_data->mpidr_to_core_pos(mpidr);
+ } else {
+ proc_num = (unsigned int)(typer_val >> TYPER_PROC_NUM_SHIFT) &
+ TYPER_PROC_NUM_MASK;
+ }
+ if (proc_num == proc_self) {
+ /* The base address doesn't need to be initialized on
+ * every warm boot.
+ */
+ if (gicv3_driver_data->rdistif_base_addrs[proc_num] != 0U)
+ return 0;
+ gicv3_driver_data->rdistif_base_addrs[proc_num] =
+ rdistif_base;
+ gicr_frame_found = true;
+ break;
+ }
+ rdistif_base += (uintptr_t)(ULL(1) << GICR_PCPUBASE_SHIFT);
+ } while ((typer_val & TYPER_LAST_BIT) == 0U);
+
+ if (!gicr_frame_found)
+ return -1;
+
+ /*
+ * Flush the driver data to ensure coherency. This is
+ * not required if platform has HW_ASSISTED_COHERENCY
+ * enabled.
+ */
+#if !HW_ASSISTED_COHERENCY
+ /*
+ * Flush the rdistif_base_addrs[] contents linked to the GICv3 driver.
+ */
+ flush_dcache_range((uintptr_t)&(gicv3_driver_data->rdistif_base_addrs[proc_num]),
+ sizeof(*(gicv3_driver_data->rdistif_base_addrs)));
+#endif
+ return 0; /* Found matching GICR frame */
+}
diff --git a/drivers/partition/gpt.c b/drivers/partition/gpt.c
index 4577f06a..1b804dee 100644
--- a/drivers/partition/gpt.c
+++ b/drivers/partition/gpt.c
@@ -52,9 +52,10 @@ int parse_gpt_entry(gpt_entry_t *gpt_entry, partition_entry_t *entry)
if (result != 0) {
return result;
}
- entry->start = (uint64_t)gpt_entry->first_lba * PARTITION_BLOCK_SIZE;
+ entry->start = (uint64_t)gpt_entry->first_lba *
+ PLAT_PARTITION_BLOCK_SIZE;
entry->length = (uint64_t)(gpt_entry->last_lba -
gpt_entry->first_lba + 1) *
- PARTITION_BLOCK_SIZE;
+ PLAT_PARTITION_BLOCK_SIZE;
return 0;
}
diff --git a/drivers/partition/partition.c b/drivers/partition/partition.c
index 7fdbf538..68133eaf 100644
--- a/drivers/partition/partition.c
+++ b/drivers/partition/partition.c
@@ -15,7 +15,7 @@
#include <drivers/partition/mbr.h>
#include <plat/common/platform.h>
-static uint8_t mbr_sector[PARTITION_BLOCK_SIZE];
+static uint8_t mbr_sector[PLAT_PARTITION_BLOCK_SIZE];
static partition_entry_list_t list;
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
@@ -57,15 +57,15 @@ static int load_mbr_header(uintptr_t image_handle, mbr_entry_t *mbr_entry)
return result;
}
result = io_read(image_handle, (uintptr_t)&mbr_sector,
- PARTITION_BLOCK_SIZE, &bytes_read);
+ PLAT_PARTITION_BLOCK_SIZE, &bytes_read);
if (result != 0) {
WARN("Failed to read data (%i)\n", result);
return result;
}
/* Check MBR boot signature. */
- if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
- (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
+ if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
+ (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
return -ENOENT;
}
offset = (uintptr_t)&mbr_sector + MBR_PRIMARY_ENTRY_OFFSET;
@@ -120,15 +120,15 @@ static int load_mbr_entry(uintptr_t image_handle, mbr_entry_t *mbr_entry,
return result;
}
result = io_read(image_handle, (uintptr_t)&mbr_sector,
- PARTITION_BLOCK_SIZE, &bytes_read);
+ PLAT_PARTITION_BLOCK_SIZE, &bytes_read);
if (result != 0) {
WARN("Failed to read data (%i)\n", result);
return result;
}
/* Check MBR boot signature. */
- if ((mbr_sector[PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
- (mbr_sector[PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
+ if ((mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 2] != MBR_SIGNATURE_FIRST) ||
+ (mbr_sector[LEGACY_PARTITION_BLOCK_SIZE - 1] != MBR_SIGNATURE_SECOND)) {
return -ENOENT;
}
offset = (uintptr_t)&mbr_sector +
generated by cgit v1.2.3 (git 2.0.4) at 2024-05-20 19:49:27 +0000