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-rw-r--r--plat/imx/imx8m/gpc_common.c9
-rw-r--r--plat/imx/imx8m/imx8mp/imx8mp_psci.c7
2 files changed, 15 insertions, 1 deletions
diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c
index 7a8837ef..62ed3ba9 100644
--- a/plat/imx/imx8m/gpc_common.c
+++ b/plat/imx/imx8m/gpc_common.c
@@ -23,6 +23,8 @@
#define FSL_SIP_CONFIG_GPC_PM_DOMAIN 0x03
#define M4_LPA_ACTIVE 0x5555
+#define DSP_LPA_ACTIVE 0xD
+#define DSP_LPA_DRAM_ACTIVE 0x1D
#define M4_LPA_IDLE 0x0
static uint32_t gpc_imr_offset[] = {
@@ -41,7 +43,12 @@ struct plat_gic_ctx imx_gicv3_ctx;
bool imx_m4_lpa_active(void)
{
- return mmio_read_32(IMX_SRC_BASE + LPA_STATUS) == M4_LPA_ACTIVE;
+ uint32_t lpa_status;
+
+ lpa_status = mmio_read_32(IMX_SRC_BASE + LPA_STATUS);
+
+ return (lpa_status == M4_LPA_ACTIVE || lpa_status == DSP_LPA_ACTIVE ||
+ lpa_status == DSP_LPA_DRAM_ACTIVE);
}
bool imx_is_m4_enabled(void)
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_psci.c b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
index 6c938b7b..2aa34e64 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_psci.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_psci.c
@@ -57,6 +57,9 @@ void imx_domain_suspend(const psci_power_state_t *target_state)
imx_anamix_override(true);
imx_noc_wrapper_pre_suspend(core_id);
} else {
+ /* flag 0xD means DSP LPA buffer is in OCRAM */
+ if (mmio_read_32(IMX_SRC_BASE + 0x98) == 0xD)
+ dram_enter_retention();
/*
* when A53 don't enter DSM, only need to
* set the system wakeup option.
@@ -78,6 +81,10 @@ void imx_domain_suspend_finish(const psci_power_state_t *target_state)
dram_exit_retention();
imx_set_sys_lpm(core_id, false);
} else {
+ /* flag 0xD means DSP LPA buffer is in OCRAM */
+ if (mmio_read_32(IMX_SRC_BASE + 0x98) == 0xD)
+ dram_exit_retention();
+
imx_set_sys_wakeup(core_id, false);
}
}