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-rw-r--r--plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c44
-rw-r--r--plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c43
-rw-r--r--plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c44
-rw-r--r--plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c45
4 files changed, 176 insertions, 0 deletions
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index cd486197..04919288 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -84,6 +84,11 @@ static const struct imx_csu_cfg csu_cfg[] = {
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+
+#if defined (CSU_RDC_TEST)
+static void csu_rdc_test(void);
+#endif
+
/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
@@ -176,6 +181,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#endif
bl31_tzc380_setup();
+
+#if defined (CSU_RDC_TEST)
+ csu_rdc_test();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -237,3 +246,38 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args) {
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif
+
+#if defined (CSU_RDC_TEST)
+static const struct imx_rdc_cfg rdc_for_test[] = {
+ /* Master domain assignment */
+
+ /* peripherals domain permission */
+
+ RDC_PDAPn(RDC_PDAP_CSU, D2R | D2W),
+
+ /* memory region */
+
+ /* Sentinel */
+ {0},
+};
+
+static const struct imx_csu_cfg csu_cfg_for_test[] = {
+ /* peripherals csl setting */
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_4, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_4, LOCKED),
+ /* master HP0~1 */
+
+ /* SA setting */
+
+ /* HP control setting */
+
+ /* Sentinel */
+ {0}
+};
+
+static void csu_rdc_test(void)
+{
+ imx_csu_init(csu_cfg_for_test);
+ imx_rdc_init(rdc_for_test);
+}
+#endif
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index f5e41d6a..841ec5a3 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -87,6 +87,10 @@ static const struct imx_csu_cfg csu_cfg[] = {
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+#if defined (CSU_RDC_TEST)
+static void csu_rdc_test(void);
+#endif
+
/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
@@ -182,6 +186,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#endif
bl31_tzc380_setup();
+
+#if defined (CSU_RDC_TEST)
+ csu_rdc_test();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -247,3 +255,38 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args) {
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif
+
+#if defined (CSU_RDC_TEST)
+static const struct imx_rdc_cfg rdc_for_test[] = {
+ /* Master domain assignment */
+
+ /* peripherals domain permission */
+
+ RDC_PDAPn(RDC_PDAP_CSU, D2R | D2W),
+
+ /* memory region */
+
+ /* Sentinel */
+ {0},
+};
+
+static const struct imx_csu_cfg csu_cfg_for_test[] = {
+ /* peripherals csl setting */
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_4, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_4, LOCKED),
+ /* master HP0~1 */
+
+ /* SA setting */
+
+ /* HP control setting */
+
+ /* Sentinel */
+ {0}
+};
+
+static void csu_rdc_test(void)
+{
+ imx_csu_init(csu_cfg_for_test);
+ imx_rdc_init(rdc_for_test);
+}
+#endif
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index 0544f93b..1e5d64da 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -86,6 +86,10 @@ static const struct imx_csu_cfg csu_cfg[] = {
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+#if defined (CSU_RDC_TEST)
+static void csu_rdc_test(void);
+#endif
+
/* get SPSR for BL33 entry */
static uint32_t get_spsr_for_bl33_entry(void)
{
@@ -181,6 +185,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#endif
bl31_tzc380_setup();
+
+#if defined (CSU_RDC_TEST)
+ csu_rdc_test();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -247,3 +255,39 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args) {
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif
+
+
+#if defined (CSU_RDC_TEST)
+static const struct imx_rdc_cfg rdc_for_test[] = {
+ /* Master domain assignment */
+
+ /* peripherals domain permission */
+
+ RDC_PDAPn(RDC_PDAP_CSU, D2R | D2W),
+
+ /* memory region */
+
+ /* Sentinel */
+ {0},
+};
+
+static const struct imx_csu_cfg csu_cfg_for_test[] = {
+ /* peripherals csl setting */
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_4, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_4, LOCKED),
+ /* master HP0~1 */
+
+ /* SA setting */
+
+ /* HP control setting */
+
+ /* Sentinel */
+ {0}
+};
+
+static void csu_rdc_test(void)
+{
+ imx_csu_init(csu_cfg_for_test);
+ imx_rdc_init(rdc_for_test);
+}
+#endif
diff --git a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
index 1a3c576f..f4c45895 100644
--- a/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mq/imx8mq_bl31_setup.c
@@ -25,7 +25,9 @@
#include <gpc.h>
#include <imx_aipstz.h>
#include <imx_uart.h>
+#include <imx_rdc.h>
#include <imx8m_caam.h>
+#include <imx8m_csu.h>
#include <plat_imx8.h>
#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
@@ -54,6 +56,10 @@ static const struct aipstz_cfg aipstz[] = {
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;
+#if defined (CSU_RDC_TEST)
+static void csu_rdc_test(void);
+#endif
+
static uint32_t imx_soc_revision;
int imx_soc_info_handler(uint32_t smc_fid, u_register_t x1, u_register_t x2,
@@ -177,6 +183,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
#endif
bl31_tzc380_setup();
+
+#if defined (CSU_RDC_TEST)
+ csu_rdc_test();
+#endif
}
void bl31_plat_arch_setup(void)
@@ -246,3 +256,38 @@ void plat_trusty_set_boot_args(aapcs64_params_t *args) {
args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
}
#endif
+
+#if defined (CSU_RDC_TEST)
+static const struct imx_rdc_cfg rdc_for_test[] = {
+ /* Master domain assignment */
+
+ /* peripherals domain permission */
+
+ RDC_PDAPn(RDC_PDAP_CSU, D2R | D2W),
+
+ /* memory region */
+
+ /* Sentinel */
+ {0},
+};
+
+static const struct imx_csu_cfg csu_cfg_for_test[] = {
+ /* peripherals csl setting */
+ CSU_CSLx(CSU_CSL_RDC, CSU_SEC_LEVEL_4, LOCKED),
+ CSU_CSLx(CSU_CSL_CSU, CSU_SEC_LEVEL_4, LOCKED),
+ /* master HP0~1 */
+
+ /* SA setting */
+
+ /* HP control setting */
+
+ /* Sentinel */
+ {0}
+};
+
+static void csu_rdc_test(void)
+{
+ imx_csu_init(csu_cfg_for_test);
+ imx_rdc_init(rdc_for_test);
+}
+#endif