diff options
| -rw-r--r-- | plat/imx/imx8mm/gpc.c | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c index 319e1054..bfa0c5c1 100644 --- a/plat/imx/imx8mm/gpc.c +++ b/plat/imx/imx8mm/gpc.c @@ -19,7 +19,6 @@ #include <fsl_sip.h> #include <soc.h> -#define GPC_MST_CPU_MAPPING 0x18 #define GPC_PGC_ACK_SEL_A53 0x24 #define GPC_IMR1_CORE0_A53 0x30 #define GPC_IMR1_CORE1_A53 0x40 @@ -35,6 +34,7 @@ #define PGC_PCR 0 +/* BSC */ #define LPCR_A53_BSC 0x0 #define LPCR_A53_BSC2 0x108 #define LPCR_M4 0x8 @@ -50,8 +50,9 @@ #define A53_LPM_STOP 0xa #define A53_CLK_ON_LPM (1 << 14) -#define SRC_GPR1_OFFSET 0x74 +#define MST_CPU_MAPPING 0x18 +#define SRC_GPR1_OFFSET 0x74 /* AD */ #define LPCR_A53_AD 0x4 @@ -612,10 +613,13 @@ void imx_gpc_init(void) val |= 0x30c00000; /* clear the MASTER0 LPM handshake */ val &= ~(1 << 6); - val &= ~(1 << 7); - val &= ~(1 << 8); mmio_write_32(IMX_GPC_BASE + LPCR_A53_BSC, val); + /* clear MASTER1&MASTER2 mapping in CPU0(A53) */ + val = mmio_read_32(IMX_GPC_BASE + MST_CPU_MAPPING); + val &= ~(0x3 << 1); + mmio_write_32(IMX_GPC_BASE + MST_CPU_MAPPING, val); + /* mask M4 DSM trigger if M4 is NOT enabled */ val = mmio_read_32(IMX_GPC_BASE + LPCR_M4); val |= 1 << 31; |