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authorSoby Mathew <soby.mathew@arm.com>2019-01-16 16:01:42 +0000
committerGitHub <noreply@github.com>2019-01-16 16:01:42 +0000
commitcd1f39b48ab4a0596ace57cc920e4d4ba6e92784 (patch)
tree3ae36f3a08f4e390048d9203748b8d178fafeb09 /services
parentedcb50abe7b4a4e168a36e12168bf5e7a8b28700 (diff)
parent434454a2710eea3f49ebfca951019d7b6c783fb5 (diff)
Merge pull request #1738 from ardbiesheuvel/synquacer-spm
synquacer: add SPM support
Diffstat (limited to 'services')
-rw-r--r--services/std_svc/spm_deprecated/spm.mk3
-rw-r--r--services/std_svc/spm_deprecated/spm_main.c2
-rw-r--r--services/std_svc/spm_deprecated/spm_setup.c14
3 files changed, 14 insertions, 5 deletions
diff --git a/services/std_svc/spm_deprecated/spm.mk b/services/std_svc/spm_deprecated/spm.mk
index ed36812f..35030206 100644
--- a/services/std_svc/spm_deprecated/spm.mk
+++ b/services/std_svc/spm_deprecated/spm.mk
@@ -21,3 +21,6 @@ SPM_SOURCES := $(addprefix services/std_svc/spm_deprecated/, \
# Let the top-level Makefile know that we intend to include a BL32 image
NEED_BL32 := yes
+
+# required so that SPM code executing at S-EL0 can access the timer registers
+NS_TIMER_SWITCH := 1
diff --git a/services/std_svc/spm_deprecated/spm_main.c b/services/std_svc/spm_deprecated/spm_main.c
index 540f257b..7525763b 100644
--- a/services/std_svc/spm_deprecated/spm_main.c
+++ b/services/std_svc/spm_deprecated/spm_main.c
@@ -151,7 +151,7 @@ static int32_t spm_init(void)
INFO("Secure Partition initialized.\n");
- return rc;
+ return !rc;
}
/*******************************************************************************
diff --git a/services/std_svc/spm_deprecated/spm_setup.c b/services/std_svc/spm_deprecated/spm_setup.c
index d458f4a6..aae6cd5e 100644
--- a/services/std_svc/spm_deprecated/spm_setup.c
+++ b/services/std_svc/spm_deprecated/spm_setup.c
@@ -84,10 +84,10 @@ void spm_sp_setup(sp_context_t *sp_ctx)
unsigned int max_granule_mask = max_granule - 1U;
/* Base must be aligned to the max granularity */
- assert((ARM_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
+ assert((PLAT_SP_IMAGE_NS_BUF_BASE & max_granule_mask) == 0);
/* Size must be a multiple of the max granularity */
- assert((ARM_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
+ assert((PLAT_SP_IMAGE_NS_BUF_SIZE & max_granule_mask) == 0);
#endif /* ENABLE_ASSERTIONS */
@@ -144,8 +144,6 @@ void spm_sp_setup(sp_context_t *sp_ctx)
SCTLR_SA0_BIT |
/* Allow cacheable data and instr. accesses to normal memory. */
SCTLR_C_BIT | SCTLR_I_BIT |
- /* Alignment fault checking enabled when at EL1 and EL0. */
- SCTLR_A_BIT |
/* Enable MMU. */
SCTLR_M_BIT
;
@@ -153,6 +151,11 @@ void spm_sp_setup(sp_context_t *sp_ctx)
sctlr_el1 &= ~(
/* Explicit data accesses at EL0 are little-endian. */
SCTLR_E0E_BIT |
+ /*
+ * Alignment fault checking disabled when at EL1 and EL0 as
+ * the UEFI spec permits unaligned accesses.
+ */
+ SCTLR_A_BIT |
/* Accesses to DAIF from EL0 are trapped to EL1. */
SCTLR_UMA_BIT
);
@@ -168,6 +171,9 @@ void spm_sp_setup(sp_context_t *sp_ctx)
write_ctx_reg(get_sysregs_ctx(ctx), CTX_VBAR_EL1,
SPM_SHIM_EXCEPTIONS_PTR);
+ write_ctx_reg(get_sysregs_ctx(ctx), CTX_CNTKCTL_EL1,
+ EL0PTEN_BIT | EL0VTEN_BIT | EL0PCTEN_BIT | EL0VCTEN_BIT);
+
/*
* FPEN: Allow the Secure Partition to access FP/SIMD registers.
* Note that SPM will not do any saving/restoring of these registers on