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| author | Soby Mathew <soby.mathew@arm.com> | 2018-12-12 09:43:49 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-12-12 09:43:49 +0000 |
| commit | 4f7812e7ac2b363d76681e57c3eb055a67815f20 (patch) | |
| tree | bd812498261de59b4e790221fc20be57074cabf2 /services | |
| parent | fca0a51ff5a710c10f4512f07d88b2e828774a3a (diff) | |
| parent | 48e1d350a0021a9a2f7e34041f28273dee9eb885 (diff) | |
Merge pull request #1712 from jeenu-arm/ssbs
AArch64: Use SSBS for CVE_2018_3639 mitigation
Diffstat (limited to 'services')
| -rw-r--r-- | services/arm_arch_svc/arm_arch_svc_setup.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/services/arm_arch_svc/arm_arch_svc_setup.c b/services/arm_arch_svc/arm_arch_svc_setup.c index 45c4704e..3a5299fd 100644 --- a/services/arm_arch_svc/arm_arch_svc_setup.c +++ b/services/arm_arch_svc/arm_arch_svc_setup.c @@ -30,9 +30,27 @@ static int32_t smccc_arch_features(u_register_t arg) return 1; return 0; /* ERRATA_APPLIES || ERRATA_MISSING */ #endif + #if WORKAROUND_CVE_2018_3639 - case SMCCC_ARCH_WORKAROUND_2: + case SMCCC_ARCH_WORKAROUND_2: { #if DYNAMIC_WORKAROUND_CVE_2018_3639 + unsigned long long ssbs; + + /* + * Firmware doesn't have to carry out dynamic workaround if the + * PE implements architectural Speculation Store Bypass Safe + * (SSBS) feature. + */ + ssbs = (read_id_aa64pfr0_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) & + ID_AA64PFR1_EL1_SSBS_MASK; + + /* + * If architectural SSBS is available on this PE, no firmware + * mitigation via SMCCC_ARCH_WORKAROUND_2 is required. + */ + if (ssbs != SSBS_UNAVAILABLE) + return 1; + /* * On a platform where at least one CPU requires * dynamic mitigation but others are either unaffected @@ -50,7 +68,11 @@ static int32_t smccc_arch_features(u_register_t arg) /* Either the CPUs are unaffected or permanently mitigated */ return SMCCC_ARCH_NOT_REQUIRED; #endif + } #endif + + /* Fallthrough */ + default: return SMC_UNK; } |