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| author | danh-arm <dan.handley@arm.com> | 2018-07-19 15:33:19 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2018-07-19 15:33:19 +0100 |
| commit | 224e1abad8723c1a2b5767c5dbe422213a486f13 (patch) | |
| tree | 2992b2b07759fb10ab2a6f290a28ce6ac786b19d /services | |
| parent | e4686fd860cedecd74d5fbd426ee154b0acfd98a (diff) | |
| parent | 1dd6c0513276ea0fa8ef1616d4ecb559eb32edba (diff) | |
Merge pull request #1481 from antonio-nino-diaz-arm/an/xlat-refactor
xlat: More refactoring
Diffstat (limited to 'services')
| -rw-r--r-- | services/std_svc/spm/sp_setup.c | 49 |
1 files changed, 13 insertions, 36 deletions
diff --git a/services/std_svc/spm/sp_setup.c b/services/std_svc/spm/sp_setup.c index b9b67f72..0d61306f 100644 --- a/services/std_svc/spm/sp_setup.c +++ b/services/std_svc/spm/sp_setup.c @@ -107,38 +107,22 @@ void spm_sp_setup(sp_context_t *sp_ctx) * MMU-related registers * --------------------- */ + xlat_ctx_t *xlat_ctx = sp_ctx->xlat_ctx_handle; - /* Set attributes in the right indices of the MAIR */ - u_register_t mair_el1 = - MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX) | - MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR, ATTR_IWBWA_OWBWA_NTR_INDEX) | - MAIR_ATTR_SET(ATTR_NON_CACHEABLE, ATTR_NON_CACHEABLE_INDEX); - - write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, mair_el1); - - /* Setup TCR_EL1. */ - u_register_t tcr_ps_bits = tcr_physical_addr_size_bits(PLAT_PHY_ADDR_SPACE_SIZE); - - u_register_t tcr_el1 = - /* Size of region addressed by TTBR0_EL1 = 2^(64-T0SZ) bytes. */ - (64 - __builtin_ctzl(PLAT_VIRT_ADDR_SPACE_SIZE)) | - /* Inner and outer WBWA, shareable. */ - TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA | TCR_RGN_INNER_WBA | - /* Set the granularity to 4KB. */ - TCR_TG0_4K | - /* Limit Intermediate Physical Address Size. */ - tcr_ps_bits << TCR_EL1_IPS_SHIFT | - /* Disable translations using TBBR1_EL1. */ - TCR_EPD1_BIT - /* The remaining fields related to TBBR1_EL1 are left as zero. */ - ; + uint64_t mmu_cfg_params[MMU_CFG_PARAM_MAX]; - tcr_el1 &= ~( - /* Enable translations using TBBR0_EL1 */ - TCR_EPD0_BIT - ); + setup_mmu_cfg((uint64_t *)&mmu_cfg_params, 0, xlat_ctx->base_table, + xlat_ctx->pa_max_address, xlat_ctx->va_max_address, + EL1_EL0_REGIME); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_MAIR_EL1, + mmu_cfg_params[MMU_CFG_MAIR]); + + write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, + mmu_cfg_params[MMU_CFG_TCR]); - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TCR_EL1, tcr_el1); + write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, + mmu_cfg_params[MMU_CFG_TTBR0]); /* Setup SCTLR_EL1 */ u_register_t sctlr_el1 = read_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1); @@ -174,13 +158,6 @@ void spm_sp_setup(sp_context_t *sp_ctx) write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_el1); - uint64_t *xlat_base = - ((xlat_ctx_t *)sp_ctx->xlat_ctx_handle)->base_table; - - /* Point TTBR0_EL1 at the tables of the context created for the SP. */ - write_ctx_reg(get_sysregs_ctx(ctx), CTX_TTBR0_EL1, - (u_register_t)xlat_base); - /* * Setup other system registers * ---------------------------- |