MLK-18732-2: Add OTP SIP service for QM/QX

Add SIP service for OTP reading/writing for use
in u-boot

Signed-off-by: Teo Hall <teo.hall@nxp.com>

5 files changed, 50 insertions, 0 deletions

diff --git a/plat/imx/common/include/fsl_sip.h b/plat/imx/common/include/fsl_sip.h
index 004349c1..4f0cec08 100644
--- a/plat/imx/common/include/fsl_sip.h
+++ b/plat/imx/common/include/fsl_sip.h
@@ -52,4 +52,8 @@
 #define FSL_SIP_WAKEUP_SRC_SCU		0x1
 #define FSL_SIP_WAKEUP_SRC_IRQSTEER	0x2
 
+#define FSL_SIP_OTP_READ		0xc200000A
+#define FSL_SIP_OTP_WRITE		0xc200000B
+
+
 #endif
diff --git a/plat/imx/common/scu_otp.c b/plat/imx/common/scu_otp.c
new file mode 100644
index 00000000..73dd7250
--- /dev/null
+++ b/plat/imx/common/scu_otp.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2018 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <debug.h>
+#include <stdlib.h>
+#include <stdint.h>
+#include <smcc_helpers.h>
+#include <std_svc.h>
+#include <types.h>
+#include <platform_def.h>
+#include <fsl_sip.h>
+#include <sci/sci.h>
+
+extern sc_ipc_t ipc_handle;
+
+int imx_otp_handler(uint32_t smc_fid,
+                    void *handle,
+                    u_register_t x1,
+                    u_register_t x2)
+{
+        int ret;
+        uint32_t fuse;
+
+        switch (smc_fid) {
+            case FSL_SIP_OTP_READ:
+                ret = sc_misc_otp_fuse_read(ipc_handle, x1, &fuse);
+                SMC_RET2(handle, ret, fuse);
+                break;
+            case FSL_SIP_OTP_WRITE:
+                ret = sc_misc_otp_fuse_write(ipc_handle, x1, x2);
+                SMC_RET1(handle, ret);
+            default:
+                ret = SMC_UNK;
+                SMC_RET1(handle, ret);
+        }
+}
+
diff --git a/plat/imx/common/sip_svc.c b/plat/imx/common/sip_svc.c
index bf774722..3899f2d9 100644
--- a/plat/imx/common/sip_svc.c
+++ b/plat/imx/common/sip_svc.c
@@ -18,6 +18,7 @@
 
 extern int imx_gpc_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
 extern int imx_cpufreq_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
+extern int imx_otp_handler(uint32_t smc_fid, void *handle, u_register_t x1, u_register_t x2);
 extern int imx_srtc_handler(uint32_t smc_fid, void *handle, u_register_t x1,
 	u_register_t x2, u_register_t x3, u_register_t x4);
 extern int lpddr4_dvfs_handler(uint32_t  smc_fid, u_register_t x1, u_register_t x2, u_register_t x3);
@@ -143,6 +144,9 @@ uintptr_t imx_svc_smc_handler(uint32_t smc_fid,
 	case  FSL_SIP_WAKEUP_SRC:
 		SMC_RET1(handle, imx_wakeup_src_handler(smc_fid, x1, x2, x3));
 		break;
+        case FSL_SIP_OTP_READ:
+        case FSL_SIP_OTP_WRITE:
+                return imx_otp_handler(smc_fid, handle, x1, x2);
 #endif
 	case  FSL_SIP_BUILDINFO:
 		SMC_RET1(handle, imx_buildinfo_handler(smc_fid, x1, x2, x3, x4));
diff --git a/plat/imx/imx8qm/platform.mk b/plat/imx/imx8qm/platform.mk
index a097a0d6..7f8afb3b 100644
--- a/plat/imx/imx8qm/platform.mk
+++ b/plat/imx/imx8qm/platform.mk
@@ -45,6 +45,7 @@ BL31_SOURCES		+=	plat/imx/common/lpuart_console.S	\
 				plat/imx/common/imx8_helpers.S		\
 				plat/imx/common/sip_svc.c		\
 				plat/imx/common/cpufreq.c		\
+				plat/imx/common/scu_otp.c		\
 				plat/imx/common/srtc.c			\
 				plat/imx/imx8qm/imx8qm_bl31_setup.c	\
 				plat/imx/imx8qm/imx8qm_psci.c		\
diff --git a/plat/imx/imx8qxp/platform.mk b/plat/imx/imx8qxp/platform.mk
index 47ced36c..bd75e745 100644
--- a/plat/imx/imx8qxp/platform.mk
+++ b/plat/imx/imx8qxp/platform.mk
@@ -44,6 +44,7 @@ BL31_SOURCES		+=	plat/imx/common/lpuart_console.S	\
 				plat/imx/common/imx8_helpers.S		\
 				plat/imx/common/sip_svc.c		\
 				plat/imx/common/cpufreq.c		\
+				plat/imx/common/scu_otp.c		\
 				plat/imx/common/srtc.c			\
 				plat/imx/imx8qxp/imx8qxp_bl31_setup.c	\
 				plat/imx/imx8qxp/imx8qxp_psci.c		\