diff options
| author | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-05-18 16:11:47 +0100 |
|---|---|---|
| committer | Sandrine Bailleux <sandrine.bailleux@arm.com> | 2016-07-08 14:37:11 +0100 |
| commit | b5fa6563e68b909dc5a364163dd745a9427eb9f4 (patch) | |
| tree | 9c87d84555142ea6940ed4ad2039824888b13b91 /plat/xilinx | |
| parent | 6f511c4782f079c75928a4dae3a4e3e4f6754831 (diff) | |
Introduce arm_setup_page_tables() function
This patch introduces the arm_setup_page_tables() function to
set up page tables on ARM platforms. It replaces the
arm_configure_mmu_elx() functions and does the same thing except
that it doesn't enable the MMU at the end. The idea is to reduce
the amount of per-EL code that is generated by the C preprocessor
by splitting the memory regions definitions and page tables creation
(which is generic) from the MMU enablement (which is the only per-EL
configuration).
As a consequence, the call to the enable_mmu_elx() function has been
moved up into the plat_arch_setup() hook. Any other ARM standard
platforms that use the functions `arm_configure_mmu_elx()` must be
updated.
Change-Id: I6f12a20ce4e5187b3849a8574aac841a136de83d
Diffstat (limited to 'plat/xilinx')
| -rw-r--r-- | plat/xilinx/zynqmp/bl31_zynqmp_setup.c | 6 | ||||
| -rw-r--r-- | plat/xilinx/zynqmp/tsp/tsp_plat_setup.c | 5 |
2 files changed, 6 insertions, 5 deletions
diff --git a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c index 6f1a18b1..2ea8b1c9 100644 --- a/plat/xilinx/zynqmp/bl31_zynqmp_setup.c +++ b/plat/xilinx/zynqmp/bl31_zynqmp_setup.c @@ -147,18 +147,18 @@ void bl31_plat_runtime_setup(void) } /* - * Perform the very early platform specific architectural setup here. At the - * moment this is only intializes the MMU in a quick and dirty way. + * Perform the very early platform specific architectural setup here. */ void bl31_plat_arch_setup(void) { plat_arm_interconnect_init(); plat_arm_interconnect_enter_coherency(); - arm_configure_mmu_el3(BL31_RO_BASE, + arm_setup_page_tables(BL31_RO_BASE, BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE, BL31_RO_BASE, BL31_RO_LIMIT, BL31_COHERENT_RAM_BASE, BL31_COHERENT_RAM_LIMIT); + enable_mmu_el3(0); } diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c index 58a3e2a1..19e2c129 100644 --- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c +++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved. * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: @@ -90,7 +90,7 @@ void tsp_platform_setup(void) ******************************************************************************/ void tsp_plat_arch_setup(void) { - arm_configure_mmu_el1(BL32_RO_BASE, + arm_setup_page_tables(BL32_RO_BASE, (BL32_END - BL32_RO_BASE), BL32_RO_BASE, BL32_RO_LIMIT @@ -99,4 +99,5 @@ void tsp_plat_arch_setup(void) BL32_COHERENT_RAM_LIMIT #endif ); + enable_mmu_el1(0); } |