diff options
| author | Andrew F. Davis <afd@ti.com> | 2019-04-25 14:02:33 -0400 |
|---|---|---|
| committer | John Tsichritzis <john.tsichritzis@arm.com> | 2019-06-06 11:20:21 +0100 |
| commit | 65f7b81728d0701e93bd13cee4e88375ec9e9b17 (patch) | |
| tree | a45a9b3b1b5d59601675f55f5f25e0e893c11648 /plat/ti | |
| parent | 49d969bbb3ca7e738bc6ef560e44c0047a9925cc (diff) | |
ti: k3: common: Use coherent memory for shared data
HW_ASSISTED_COHERENCY implies something stronger than just hardware
coherent interconnect, specifically a DynamIQ capable ARM core.
For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early
and then let the caches get shut off on powerdown, to prevent data
corruption we also need to USE_COHERENT_MEM so that any accesses to
shared memory after this point is only to memory that is set as
non-cached for all cores.
Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949
Signed-off-by: Andrew F. Davis <afd@ti.com>
Diffstat (limited to 'plat/ti')
| -rw-r--r-- | plat/ti/k3/common/plat_common.mk | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk index 2e5f5845..3613a0e2 100644 --- a/plat/ti/k3/common/plat_common.mk +++ b/plat/ti/k3/common/plat_common.mk @@ -12,8 +12,8 @@ COLD_BOOT_SINGLE_CPU := 1 PROGRAMMABLE_RESET_ADDRESS:= 1 # System coherency is managed in hardware -HW_ASSISTED_COHERENCY := 1 -USE_COHERENT_MEM := 0 +WARMBOOT_ENABLE_DCACHE_EARLY := 1 +USE_COHERENT_MEM := 1 # A53 erratum for SoC. (enable them all) ERRATA_A53_826319 := 1 |