diff options
| author | Yann Gautier <yann.gautier@st.com> | 2019-01-17 14:52:47 +0100 |
|---|---|---|
| committer | Yann Gautier <yann.gautier@st.com> | 2019-01-18 15:45:08 +0100 |
| commit | 88ef0425da07672bd2e20f548533bdf6f258d888 (patch) | |
| tree | ee24c0816f6338d3812f516da8b4f0b743b3b58e /plat/st | |
| parent | a42bad37639b34f4191959e604c7ee61a7d02109 (diff) | |
stm32mp1: add BSEC driver
The BSEC (Boot and Security and OTP control) is intended to control an OTP
(one time programmable) fuse box, used for on-chip non-volatile storage
for device configuration and security parameters.
Change-Id: I38c44684c7b9c6a1f24ec0ae3fe99cec481d5a51
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
Signed-off-by: Mathieu Belou <mathieu.belou@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Diffstat (limited to 'plat/st')
| -rw-r--r-- | plat/st/stm32mp1/platform.mk | 1 | ||||
| -rw-r--r-- | plat/st/stm32mp1/stm32mp1_def.h | 15 |
2 files changed, 16 insertions, 0 deletions
diff --git a/plat/st/stm32mp1/platform.mk b/plat/st/stm32mp1/platform.mk index b5a7a79a..4288f23d 100644 --- a/plat/st/stm32mp1/platform.mk +++ b/plat/st/stm32mp1/platform.mk @@ -47,6 +47,7 @@ PLAT_BL_COMMON_SOURCES += ${LIBFDT_SRCS} \ drivers/arm/tzc/tzc400.c \ drivers/delay_timer/delay_timer.c \ drivers/delay_timer/generic_delay_timer.c \ + drivers/st/bsec/bsec.c \ drivers/st/clk/stm32mp1_clk.c \ drivers/st/clk/stm32mp1_clkfunc.c \ drivers/st/ddr/stm32mp1_ddr_helpers.c \ diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h index 0dd72157..8cd5aeb2 100644 --- a/plat/st/stm32mp1/stm32mp1_def.h +++ b/plat/st/stm32mp1/stm32mp1_def.h @@ -203,6 +203,21 @@ enum ddr_type { #define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ 52000000 /*52 MHz*/ /******************************************************************************* + * STM32MP1 BSEC / OTP + ******************************************************************************/ +#define STM32MP1_OTP_MAX_ID 0x5FU +#define STM32MP1_UPPER_OTP_START 0x20U + +#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U) + +/* OTP offsets */ +#define DATA0_OTP U(0) + +/* OTP mask */ +/* DATA0 */ +#define DATA0_OTP_SECURED BIT(6) + +/******************************************************************************* * STM32MP1 TAMP ******************************************************************************/ #define TAMP_BASE U(0x5C00A000) |