diff options
| author | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-08-24 16:30:29 +0100 |
|---|---|---|
| committer | Antonio Nino Diaz <antonio.ninodiaz@arm.com> | 2018-08-30 09:22:33 +0100 |
| commit | c9512bca3b69dcb50ac839ce1f6d24a68be46986 (patch) | |
| tree | 9eacb4a8d992cf64f1bd719134baf8eb31292251 /plat/socionext | |
| parent | 2a7c9e15c23b376121747ccae78bef91db6225ba (diff) | |
Fix MISRA defects in BL31 common code
Change-Id: I5993b425445ee794e6d2a792c244c0af53640655
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
Diffstat (limited to 'plat/socionext')
| -rw-r--r-- | plat/socionext/synquacer/sq_bl31_setup.c | 2 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_bl31_setup.c | 5 |
2 files changed, 3 insertions, 4 deletions
diff --git a/plat/socionext/synquacer/sq_bl31_setup.c b/plat/socionext/synquacer/sq_bl31_setup.c index 30d06e9e..26b8ff1b 100644 --- a/plat/socionext/synquacer/sq_bl31_setup.c +++ b/plat/socionext/synquacer/sq_bl31_setup.c @@ -137,7 +137,7 @@ void bl31_platform_setup(void) /* Enable and initialize the System level generic timer */ mmio_write_32(SQ_SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0) | CNTCR_EN); + CNTCR_FCREQ(0U) | CNTCR_EN); /* Allow access to the System counter timer module */ sq_configure_sys_timer(); diff --git a/plat/socionext/uniphier/uniphier_bl31_setup.c b/plat/socionext/uniphier/uniphier_bl31_setup.c index d9c87bd9..9e28eecd 100644 --- a/plat/socionext/uniphier/uniphier_bl31_setup.c +++ b/plat/socionext/uniphier/uniphier_bl31_setup.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -17,7 +17,6 @@ #include "uniphier.h" -#define BL31_END (unsigned long)(&__BL31_END__) #define BL31_SIZE ((BL31_END) - (BL31_BASE)) static entry_point_info_t bl32_image_ep_info; @@ -70,7 +69,7 @@ void bl31_platform_setup(void) /* Enable and initialize the System level generic timer */ mmio_write_32(UNIPHIER_SYS_CNTCTL_BASE + CNTCR_OFF, - CNTCR_FCREQ(0) | CNTCR_EN); + CNTCR_FCREQ(0U) | CNTCR_EN); } void bl31_plat_arch_setup(void) |