diff options
| author | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-01-22 18:35:16 +0900 |
|---|---|---|
| committer | Masahiro Yamada <yamada.masahiro@socionext.com> | 2018-01-24 21:36:24 +0900 |
| commit | 8e053dc5ebb5d99ef6e2605e2d57c202123717d4 (patch) | |
| tree | 9a123f567094dc382594b01d13a4095fae8d2b40 /plat/socionext | |
| parent | d2184052ec9f7055e666885d2e9f1c563bdd8d93 (diff) | |
uniphier: set PROGRAMMABLE_RESET_ADDRESS to disable warm boot mailbox
The warm boot mailbox code is compiled if PROGRAMMABLE_RESET_ADDRESS
is disabled.
The warm boot mailbox is useless for UniPhier SoC family because BL1
is not the first image. The UniPhier platform implements non-TF ROM,
then BL1 works as a pseudo ROM, so it is never executed in the warm
boot.
The reset vector address is not actually programmable for UniPhier
platform, but it should not hurt to enable PROGRAMMABLE_RESET_ADDRESS
to disable the mailbox and remove pointless plat_get_my_entrypoint.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'plat/socionext')
| -rw-r--r-- | plat/socionext/uniphier/platform.mk | 16 | ||||
| -rw-r--r-- | plat/socionext/uniphier/uniphier_bl1_helpers.S | 15 |
2 files changed, 8 insertions, 23 deletions
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk index e0ddfa82..1d7be398 100644 --- a/plat/socionext/uniphier/platform.mk +++ b/plat/socionext/uniphier/platform.mk @@ -1,15 +1,16 @@ # -# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. +# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved. # # SPDX-License-Identifier: BSD-3-Clause # -override COLD_BOOT_SINGLE_CPU := 1 -override ENABLE_PLAT_COMPAT := 0 -override LOAD_IMAGE_V2 := 1 -override USE_COHERENT_MEM := 1 -override USE_TBBR_DEFS := 1 -override ENABLE_SVE_FOR_NS := 0 +override COLD_BOOT_SINGLE_CPU := 1 +override ENABLE_PLAT_COMPAT := 0 +override LOAD_IMAGE_V2 := 1 +override PROGRAMMABLE_RESET_ADDRESS := 1 +override USE_COHERENT_MEM := 1 +override USE_TBBR_DEFS := 1 +override ENABLE_SVE_FOR_NS := 0 # Cortex-A53 revision r0p4-51rel0 # needed for LD20, unneeded for LD11, PXs3 (no ACE) @@ -48,7 +49,6 @@ PLAT_BL_COMMON_SOURCES += drivers/console/aarch64/console.S \ BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \ lib/cpus/aarch64/cortex_a72.S \ - $(PLAT_PATH)/uniphier_bl1_helpers.S \ $(PLAT_PATH)/uniphier_bl1_setup.c \ $(IO_SOURCES) diff --git a/plat/socionext/uniphier/uniphier_bl1_helpers.S b/plat/socionext/uniphier/uniphier_bl1_helpers.S deleted file mode 100644 index 58185657..00000000 --- a/plat/socionext/uniphier/uniphier_bl1_helpers.S +++ /dev/null @@ -1,15 +0,0 @@ -/* - * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#include <arch.h> -#include <asm_macros.S> - - .globl plat_get_my_entrypoint - -func plat_get_my_entrypoint - mov x0, #0 - ret -endfunc plat_get_my_entrypoint |