uniphier: switch to BL2-AT-EL3 and remove BL1 support

UniPhier platform implements non-TF boot ROM.  Prior to the BL2-AT-EL3
support, BL1 (worked as a pseudo ROM) was needed just for ensuring BL2
is entered at EL1-S.  Now, this platform is able to avoid this waste.

Enable the BL2_AT_EL3 option, and remove BL1.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>

5 files changed, 36 insertions, 106 deletions

diff --git a/plat/socionext/uniphier/include/platform_def.h b/plat/socionext/uniphier/include/platform_def.h
index cc046eb4..546670e0 100644
--- a/plat/socionext/uniphier/include/platform_def.h
+++ b/plat/socionext/uniphier/include/platform_def.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -27,29 +27,20 @@
 #define PLAT_MAX_OFF_STATE		2
 #define PLAT_MAX_RET_STATE		1
 
-#define UNIPHIER_SEC_DRAM_BASE		0x81000000
+#define UNIPHIER_SEC_DRAM_BASE		0x80000000
 #define UNIPHIER_SEC_DRAM_LIMIT		0x82000000
 #define UNIPHIER_SEC_DRAM_SIZE		((UNIPHIER_SEC_DRAM_LIMIT) - \
 					 (UNIPHIER_SEC_DRAM_BASE))
 
-#define BL1_RO_BASE			0x80000000
-#define BL1_RO_LIMIT			0x80018000
-#define BL1_RW_LIMIT			(UNIPHIER_SEC_DRAM_LIMIT)
-#define BL1_RW_BASE			((BL1_RW_LIMIT) - 0x00040000)
+#define BL2_BASE			(UNIPHIER_SEC_DRAM_BASE)
+#define BL2_LIMIT			((BL2_BASE) + 0x00020000)
 
-#define BL2_LIMIT			(BL1_RW_BASE)
-#define BL2_BASE			((BL2_LIMIT) - 0x00040000)
-
-#define BL31_BASE			(UNIPHIER_SEC_DRAM_BASE)
+#define BL31_BASE			(BL2_LIMIT)
 #define BL31_LIMIT			((BL31_BASE) + 0x00080000)
 
 #define BL32_BASE			(BL31_LIMIT)
 #define BL32_LIMIT			(UNIPHIER_SEC_DRAM_LIMIT)
 
-#define UNIPHIER_BLOCK_BUF_SIZE		0x00400000
-#define UNIPHIER_BLOCK_BUF_BASE		((BL2_BASE) - \
-					 (UNIPHIER_BLOCK_BUF_SIZE))
-
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 32)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 32)
 
@@ -63,7 +54,6 @@
 
 #define TSP_SEC_MEM_BASE		(BL32_BASE)
 #define TSP_SEC_MEM_SIZE		((BL32_LIMIT) - (BL32_BASE))
-#define TSP_PROGBITS_LIMIT		(UNIPHIER_BLOCK_BUF_BASE)
 #define TSP_IRQ_SEC_PHY_TIMER		29
 
 #endif /* __PLATFORM_DEF_H__ */
diff --git a/plat/socionext/uniphier/platform.mk b/plat/socionext/uniphier/platform.mk
index 1d7be398..18b56a0b 100644
--- a/plat/socionext/uniphier/platform.mk
+++ b/plat/socionext/uniphier/platform.mk
@@ -4,6 +4,7 @@
 # SPDX-License-Identifier: BSD-3-Clause
 #
 
+override BL2_AT_EL3			:= 1
 override COLD_BOOT_SINGLE_CPU		:= 1
 override ENABLE_PLAT_COMPAT		:= 0
 override LOAD_IMAGE_V2			:= 1
@@ -28,18 +29,7 @@ include lib/xlat_tables_v2/xlat_tables.mk
 PLAT_PATH		:=	plat/socionext/uniphier
 PLAT_INCLUDES		:=	-I$(PLAT_PATH)/include
 
-# IO sources for BL1, BL2
-IO_SOURCES		:=	drivers/io/io_block.c			\
-				drivers/io/io_fip.c			\
-				drivers/io/io_memmap.c			\
-				drivers/io/io_storage.c			\
-				$(PLAT_PATH)/uniphier_boot_device.c	\
-				$(PLAT_PATH)/uniphier_emmc.c		\
-				$(PLAT_PATH)/uniphier_io_storage.c	\
-				$(PLAT_PATH)/uniphier_nand.c		\
-				$(PLAT_PATH)/uniphier_usb.c
-
-# common sources for BL1, BL2, BL31
+# common sources for BL2, BL31 (and BL32 if SPD=tspd)
 PLAT_BL_COMMON_SOURCES	+=	drivers/console/aarch64/console.S	\
 				$(PLAT_PATH)/uniphier_console.S		\
 				$(PLAT_PATH)/uniphier_helpers.S		\
@@ -47,16 +37,21 @@ PLAT_BL_COMMON_SOURCES	+=	drivers/console/aarch64/console.S	\
 				$(PLAT_PATH)/uniphier_xlat_setup.c	\
 				${XLAT_TABLES_LIB_SRCS}
 
-BL1_SOURCES		+=	lib/cpus/aarch64/cortex_a53.S		\
-				lib/cpus/aarch64/cortex_a72.S		\
-				$(PLAT_PATH)/uniphier_bl1_setup.c	\
-				$(IO_SOURCES)
-
 BL2_SOURCES		+=	common/desc_image_load.c		\
+				drivers/io/io_block.c			\
+				drivers/io/io_fip.c			\
+				drivers/io/io_memmap.c			\
+				drivers/io/io_storage.c			\
+				lib/cpus/aarch64/cortex_a53.S		\
+				lib/cpus/aarch64/cortex_a72.S		\
 				$(PLAT_PATH)/uniphier_bl2_setup.c	\
+				$(PLAT_PATH)/uniphier_boot_device.c	\
+				$(PLAT_PATH)/uniphier_emmc.c		\
 				$(PLAT_PATH)/uniphier_image_desc.c	\
+				$(PLAT_PATH)/uniphier_io_storage.c	\
+				$(PLAT_PATH)/uniphier_nand.c		\
 				$(PLAT_PATH)/uniphier_scp.c		\
-				$(IO_SOURCES)
+				$(PLAT_PATH)/uniphier_usb.c
 
 BL31_SOURCES		+=	drivers/arm/cci/cci.c			\
 				drivers/arm/gic/common/gic_common.c	\
@@ -82,7 +77,7 @@ include drivers/auth/mbedtls/mbedtls_x509.mk
 
 PLAT_INCLUDES		+=	-Iinclude/common/tbbr
 
-TBB_SOURCES		:=	drivers/auth/auth_mod.c			\
+BL2_SOURCES		+=	drivers/auth/auth_mod.c			\
 				drivers/auth/crypto_mod.c		\
 				drivers/auth/img_parser_mod.c		\
 				drivers/auth/tbbr/tbbr_cot.c		\
@@ -90,14 +85,10 @@ TBB_SOURCES		:=	drivers/auth/auth_mod.c			\
 				$(PLAT_PATH)/uniphier_rotpk.S		\
 				$(PLAT_PATH)/uniphier_tbbr.c
 
-BL1_SOURCES		+=	$(TBB_SOURCES)
-BL2_SOURCES		+=	$(TBB_SOURCES)
-
 ROT_KEY			= $(BUILD_PLAT)/rot_key.pem
 ROTPK_HASH		= $(BUILD_PLAT)/rotpk_sha256.bin
 
 $(eval $(call add_define_val,ROTPK_HASH,'"$(ROTPK_HASH)"'))
-$(BUILD_PLAT)/bl1/uniphier_rotpk.o: $(ROTPK_HASH)
 $(BUILD_PLAT)/bl2/uniphier_rotpk.o: $(ROTPK_HASH)
 
 certificates: $(ROT_KEY)
@@ -112,8 +103,8 @@ $(ROTPK_HASH): $(ROT_KEY)
 
 endif
 
-.PHONY: bl1_gzip
-bl1_gzip: $(BUILD_PLAT)/bl1.bin.gzip
-%.gzip: %
+.PHONY: bl2_gzip
+bl2_gzip: $(BUILD_PLAT)/bl2.bin.gz
+%.gz: %
 	@echo "  GZIP    $@"
 	$(Q)gzip -n -f -9 $< --stdout > $@
diff --git a/plat/socionext/uniphier/uniphier.h b/plat/socionext/uniphier/uniphier.h
index 95b29b8f..2af30dff 100644
--- a/plat/socionext/uniphier/uniphier.h
+++ b/plat/socionext/uniphier/uniphier.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -67,7 +67,9 @@ void uniphier_gic_pcpu_init(void);
 unsigned int uniphier_calc_core_pos(u_register_t mpidr);
 
 #define UNIPHIER_NS_DRAM_BASE		0x84000000
-#define UNIPHIER_NS_DRAM_SIZE		0x01000000
+#define UNIPHIER_NS_DRAM_LIMIT		0x85000000
+#define UNIPHIER_NS_DRAM_SIZE		((UNIPHIER_NS_DRAM_LIMIT) - \
+					 (UNIPHIER_NS_DRAM_BASE))
 
 #define UNIPHIER_BL33_BASE		(UNIPHIER_NS_DRAM_BASE)
 #define UNIPHIER_BL33_MAX_SIZE		0x00100000
@@ -76,4 +78,9 @@ unsigned int uniphier_calc_core_pos(u_register_t mpidr);
 					 (UNIPHIER_BL33_MAX_SIZE))
 #define UNIPHIER_SCP_MAX_SIZE		0x00020000
 
+#define UNIPHIER_BLOCK_BUF_BASE		((UNIPHIER_SCP_BASE) + \
+					 (UNIPHIER_SCP_MAX_SIZE))
+#define UNIPHIER_BLOCK_BUF_SIZE		((UNIPHIER_NS_DRAM_LIMIT) - \
+					 (UNIPHIER_BLOCK_BUF_BASE))
+
 #endif /* __UNIPHIER_H__ */
diff --git a/plat/socionext/uniphier/uniphier_bl1_setup.c b/plat/socionext/uniphier/uniphier_bl1_setup.c
deleted file mode 100644
index da7740ad..00000000
--- a/plat/socionext/uniphier/uniphier_bl1_setup.c
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch_helpers.h>
-#include <bl_common.h>
-#include <console.h>
-#include <debug.h>
-#include <errno.h>
-#include <platform.h>
-#include <platform_def.h>
-#include <xlat_mmu_helpers.h>
-
-#include "uniphier.h"
-
-void bl1_early_platform_setup(void)
-{
-	uniphier_console_setup();
-}
-
-void bl1_plat_arch_setup(void)
-{
-	uniphier_mmap_setup(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
-			    NULL);
-	enable_mmu_el3(0);
-}
-
-void bl1_platform_setup(void)
-{
-	unsigned int soc;
-	int ret;
-
-	soc = uniphier_get_soc_id();
-	if (soc == UNIPHIER_SOC_UNKNOWN) {
-		ERROR("unsupported SoC\n");
-		plat_error_handler(-ENOTSUP);
-	}
-
-	ret = uniphier_io_setup(soc);
-	if (ret) {
-		ERROR("failed to setup io devices\n");
-		plat_error_handler(ret);
-	}
-}
-
-static meminfo_t uniphier_tzram_layout = {
-	.total_base = UNIPHIER_SEC_DRAM_BASE,
-	.total_size = UNIPHIER_SEC_DRAM_SIZE,
-};
-
-meminfo_t *bl1_plat_sec_mem_layout(void)
-{
-	return &uniphier_tzram_layout;
-}
diff --git a/plat/socionext/uniphier/uniphier_bl2_setup.c b/plat/socionext/uniphier/uniphier_bl2_setup.c
index b83e7002..daf0c45d 100644
--- a/plat/socionext/uniphier/uniphier_bl2_setup.c
+++ b/plat/socionext/uniphier/uniphier_bl2_setup.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -15,13 +15,11 @@
 
 #include "uniphier.h"
 
-static meminfo_t uniphier_bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
 static int uniphier_bl2_kick_scp;
 
-void bl2_early_platform_setup(meminfo_t *mem_layout)
+void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
+				  u_register_t x2, u_register_t x3)
 {
-	uniphier_bl2_tzram_layout = *mem_layout;
-
 	uniphier_console_setup();
 }
 
@@ -32,7 +30,7 @@ static const struct mmap_region uniphier_bl2_mmap[] = {
 	{ .size = 0 },
 };
 
-void bl2_plat_arch_setup(void)
+void bl2_el3_plat_arch_setup(void)
 {
 	unsigned int soc;
 	int skip_scp = 0;
@@ -40,7 +38,7 @@ void bl2_plat_arch_setup(void)
 
 	uniphier_mmap_setup(UNIPHIER_SEC_DRAM_BASE, UNIPHIER_SEC_DRAM_SIZE,
 			    uniphier_bl2_mmap);
-	enable_mmu_el1(0);
+	enable_mmu_el3(0);
 
 	soc = uniphier_get_soc_id();
 	if (soc == UNIPHIER_SOC_UNKNOWN) {