diff options
| author | Heiko Stuebner <heiko@sntech.de> | 2019-05-29 12:03:38 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2019-05-29 12:06:30 +0200 |
| commit | 3e6945e919608bb071de6006a048853a2ea07c66 (patch) | |
| tree | 2dcbb5e15ca8f4fa12d73b762b8b827d93a4f080 /plat/rockchip | |
| parent | 89a4d269146c90e944ea36d4afb39b27d82b23e2 (diff) | |
rockchip: drop rockchip-specific imported linker symbols for bl31
In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are
currently imported into special BL31_RO_* constants while the general
code also imports them as BL_CODE_BASE and BL_CODE_END.
So we can just use the general symbols and can drop the duplication.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/common/bl31_plat_setup.c | 17 |
1 files changed, 4 insertions, 13 deletions
diff --git a/plat/rockchip/common/bl31_plat_setup.c b/plat/rockchip/common/bl31_plat_setup.c index 30782d1d..18f8dd91 100644 --- a/plat/rockchip/common/bl31_plat_setup.c +++ b/plat/rockchip/common/bl31_plat_setup.c @@ -18,15 +18,6 @@ #include <plat_private.h> #include <plat/common/platform.h> -/* - * The next 2 constants identify the extents of the code & RO data region. - * These addresses are used by the MMU setup code and therefore they must be - * page-aligned. It is the responsibility of the linker script to ensure that - * __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses. - */ -IMPORT_SYM(unsigned long, __RO_START__, BL31_RO_BASE); -IMPORT_SYM(unsigned long, __RO_END__, BL31_RO_LIMIT); - static entry_point_info_t bl32_ep_info; static entry_point_info_t bl33_ep_info; @@ -116,10 +107,10 @@ void bl31_plat_arch_setup(void) { plat_cci_init(); plat_cci_enable(); - plat_configure_mmu_el3(BL31_RO_BASE, - BL_COHERENT_RAM_END - BL31_RO_BASE, - BL31_RO_BASE, - BL31_RO_LIMIT, + plat_configure_mmu_el3(BL_CODE_BASE, + BL_COHERENT_RAM_END - BL_CODE_BASE, + BL_CODE_BASE, + BL_CODE_END, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END); } |