diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-12-30 13:53:25 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:44 +0800 |
| commit | 87b5c17f915e3eccb4711e2adcf4e22cbb8af101 (patch) | |
| tree | 0d0c509b0589cac2ad68354a778d6383b63ab7de /plat/rockchip | |
| parent | 175476f9e561704ab309c60cba531d95b1c0aa6b (diff) | |
rockchip: rk3399: fix PMU_CRU_GATEDIS_CON0 setting error
As rk3399 TRM1.1 document show, when set PMU_CRU_GATEDIS_CON0/1
register, it need set the write_mask bit (bit16 ~ bit31), but as
we test, it not need it. So need to correct the setting way, otherwise
it will set wrong value to this register.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/m0_ctl.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c index 66f3a19c..47bd3e3d 100644 --- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c @@ -52,9 +52,8 @@ void m0_init(void) BITS_WITH_WMASK((M0_BINCODE_BASE >> 28) & 0xf, 0xf, 0)); - /* gating disable for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, - BITS_WITH_WMASK(0x3, 0x3, 0)); + /* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */ + mmio_setbits_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, 0x02); /* * To switch the parent to xin24M and div == 1, |