diff options
| author | Derek Basehore <dbasehore@chromium.org> | 2017-05-06 23:22:23 -0700 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2017-06-08 09:59:53 +0800 |
| commit | 7d1b3f5a9ac3a21b004f13a0752c8f4ebffb71bd (patch) | |
| tree | 41fb9ec91f39d7d849e8d0dc3afd8e591838aacc /plat/rockchip | |
| parent | 60400fc8689c28b3e0f3012cb3a14e92e392e07f (diff) | |
rockchip/rk3399: remove unneeded DDR restore function
This removes the phy_dll_bypass_set function as it is unneeded. The
values that function sets are saved during suspend, so the proper
values will be restored on resume.
Change-Id: I17542206c56e639ce8cb6375233145167441d4e2
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/suspend.c | 26 |
1 files changed, 0 insertions, 26 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index d6d5eb0f..3aba57ca 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -119,31 +119,6 @@ static __sramfunc void phy_pctrl_reset(uint32_t ch) sram_udelay(10); } -static __sramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t hz) -{ - if (hz <= 125 * MHz) { - /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - mmio_setbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8); - mmio_setbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8); - mmio_setbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8); - mmio_setbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8); - /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - mmio_setbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16); - mmio_setbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16); - mmio_setbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16); - } else { - /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */ - mmio_clrbits_32(PHY_REG(ch, 86), (0x3 << 2) << 8); - mmio_clrbits_32(PHY_REG(ch, 214), (0x3 << 2) << 8); - mmio_clrbits_32(PHY_REG(ch, 342), (0x3 << 2) << 8); - mmio_clrbits_32(PHY_REG(ch, 470), (0x3 << 2) << 8); - /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */ - mmio_clrbits_32(PHY_REG(ch, 547), (0x3 << 2) << 16); - mmio_clrbits_32(PHY_REG(ch, 675), (0x3 << 2) << 16); - mmio_clrbits_32(PHY_REG(ch, 803), (0x3 << 2) << 16); - } -} - static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) { /* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */ @@ -721,7 +696,6 @@ __sramfunc void dmc_restore(void) retry: for (channel = 0; channel < sdram_params->num_channels; channel++) { phy_pctrl_reset(channel); - phy_dll_bypass_set(channel, sdram_params->ddr_freq); if (channel >= sdram_params->num_channels) continue; |