diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-09 14:51:38 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:45 +0800 |
| commit | 43f52e92e45823c6967b20fb9e90dd6e3dc7275f (patch) | |
| tree | b8c92bd08a1f4a292112b2205db090d7b1f115ad /plat/rockchip | |
| parent | 50bde47fe3f861a707d48cb36e556369a03f36f6 (diff) | |
rockchip: rk3399: disable training modules after DDR DFS
On resume, we use the DFS hardware to switch frequency index,
followed by a full training sequence on that index. Leaving
the DFS training modules enabled causes issues with the full
training done at resume. We also only needs these enabled
during a call to ddr_set_rate during runtime, so there's no
issue disabling them at the end of ddr_set_rate.
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dfs.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index c15528e8..37f666a5 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1021,6 +1021,17 @@ static void gen_rk3399_enable_training(uint32_t ch_cnt, uint32_t nmhz) } } +static void gen_rk3399_disable_training(uint32_t ch_cnt) +{ + uint32_t i; + + for (i = 0; i < ch_cnt; i++) { + mmio_clrbits_32(CTL_REG(i, 305), 1 << 16); + mmio_clrbits_32(CTL_REG(i, 71), 1); + mmio_clrbits_32(CTL_REG(i, 70), 1 << 8); + } +} + static void gen_rk3399_ctl_params(struct timing_related_config *timing_config, struct dram_timing_t *pdram_timing, uint32_t fn) @@ -2019,7 +2030,7 @@ uint32_t ddr_set_rate(uint32_t hz) if (mhz == rk3399_dram_status.index_freq[rk3399_dram_status.current_index]) - goto out; + return mhz; index = to_get_clk_index(mhz); mhz = dpll_rates_table[index].mhz; @@ -2046,6 +2057,7 @@ uint32_t ddr_set_rate(uint32_t hz) low_power = rk3399_dram_status.low_power_stat; resume_low_power(low_power); out: + gen_rk3399_disable_training(rk3399_dram_status.timing_config.ch_cnt); return mhz; } |