diff options
| author | Xing Zheng <zhengxing@rock-chips.com> | 2016-12-20 20:44:41 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:44 +0800 |
| commit | 175476f9e561704ab309c60cba531d95b1c0aa6b (patch) | |
| tree | f63f0740a57f260550fc9a87c4caa6ff45afc846 /plat/rockchip | |
| parent | ca9286c68a8fe408912fc1cd1b1e1789339ce135 (diff) | |
FIXUP: rockchip: rk3399: fix the incorrect bit during m0_init
We found that the DUT will be hanged if we don't set the bit_1 of the
PMUCRU_GATEDIS_CON0. But, from the TRM, there is weird that the bit_1
is set the clk_center1_gating_dis, not clk_pmum0_gating_dis. Is the
TRM incorrect? We need to check it with the IC team and re-clean the
commit message and explain it tomorrow.
Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/pmu/m0_ctl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c index 11bc0eae..66f3a19c 100644 --- a/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c +++ b/plat/rockchip/rk3399/drivers/pmu/m0_ctl.c @@ -53,7 +53,8 @@ void m0_init(void) 0xf, 0)); /* gating disable for M0 */ - mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, BIT_WITH_WMSK(0)); + mmio_write_32(PMUCRU_BASE + PMUCRU_GATEDIS_CON0, + BITS_WITH_WMASK(0x3, 0x3, 0)); /* * To switch the parent to xin24M and div == 1, |