diff options
| author | Lin Huang <hl@rock-chips.com> | 2016-12-15 15:08:47 +0800 |
|---|---|---|
| committer | Xing Zheng <zhengxing@rock-chips.com> | 2017-02-24 20:07:44 +0800 |
| commit | 09f41f8ed68de101702a1045ea2570d6f6975fa3 (patch) | |
| tree | d0e0ab1418d5df9b075b361d53f2e5ab405f9f87 /plat/rockchip | |
| parent | 46b9dbce2f4ee16e91d10f5abe825e45b2009a9b (diff) | |
rockchip: rk3399: dram: set all ddr frequency pll_postdiv values to 0
The phy pll needs to get 2X frequency to the DDR, so set the
pll_postdiv to 0.
Signed-off-by: Lin Huang <hl@rock-chips.com>
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/dfs.c | 20 |
1 files changed, 2 insertions, 18 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/dfs.c b/plat/rockchip/rk3399/drivers/dram/dfs.c index b4aa3f9f..77cb07f8 100644 --- a/plat/rockchip/rk3399/drivers/dram/dfs.c +++ b/plat/rockchip/rk3399/drivers/dram/dfs.c @@ -1545,15 +1545,7 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, /* DENALI_PHY_911 13bits offset_0 */ /* PHY_LP4_BOOT_PLL_CTRL */ /* DENALI_PHY_919 13bits offset_0 */ - if (pdram_timing->mhz <= 150) - tmp = 3; - else if (pdram_timing->mhz <= 300) - tmp = 2; - else if (pdram_timing->mhz <= 600) - tmp = 1; - else - tmp = 0; - tmp = (1 << 12) | (tmp << 9) | (2 << 7) | (1 << 1); + tmp = (1 << 12) | (2 << 7) | (1 << 1); mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff, tmp); mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff, tmp); @@ -1561,15 +1553,7 @@ static void gen_rk3399_phy_params(struct timing_related_config *timing_config, /* DENALI_PHY_911 13bits offset_16 */ /* PHY_LP4_BOOT_PLL_CTRL_CA */ /* DENALI_PHY_919 13bits offset_16 */ - if (pdram_timing->mhz <= 150) - tmp = 3; - else if (pdram_timing->mhz <= 300) - tmp = 2; - else if (pdram_timing->mhz <= 600) - tmp = 1; - else - tmp = 0; - tmp = (tmp << 9) | (2 << 7) | (1 << 5) | (1 << 1); + tmp = (2 << 7) | (1 << 5) | (1 << 1); mmio_clrsetbits_32(PHY_REG(i, 911), 0x1fff << 16, tmp << 16); mmio_clrsetbits_32(PHY_REG(i, 919), 0x1fff << 16, tmp << 16); |