diff options
| author | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-05 14:54:46 -0700 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2017-06-14 15:00:13 -0700 |
| commit | fb7d32e5881ef2445e8fe2305005f5590d4a7cfa (patch) | |
| tree | 24c77f58069dddfc1e8c530d06f9bf94bc77f613 /plat/rockchip | |
| parent | 6311f63de02ee04d93016242977ade4727089de8 (diff) | |
Unique names for defines in the CPU libraries
This patch makes all the defines in the CPU libraries unique,
by prefixing them with the CPU name.
NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE
TO START USING THE UPDATED NAMES
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/common/aarch64/plat_helpers.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/plat/rockchip/common/aarch64/plat_helpers.S b/plat/rockchip/common/aarch64/plat_helpers.S index 8a7be740..1c8aefcb 100644 --- a/plat/rockchip/common/aarch64/plat_helpers.S +++ b/plat/rockchip/common/aarch64/plat_helpers.S @@ -43,9 +43,9 @@ handler_a72: * Set the L2 Data RAM latency for Cortex-A72. * Set the L2 Tag RAM latency to for Cortex-A72. */ - mov x0, #((5 << L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ + mov x0, #((5 << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT) | \ (0x1 << 5)) - msr L2CTLR_EL1, x0 + msr CORTEX_A72_L2CTLR_EL1, x0 isb handler_end: ret |