diff options
| author | Derek Basehore <dbasehore@chromium.org> | 2017-05-12 21:29:13 -0700 |
|---|---|---|
| committer | Caesar Wang <wxt@rock-chips.com> | 2017-06-08 09:59:53 +0800 |
| commit | c82eef6ce57a5d1f8408778f191928e958c39878 (patch) | |
| tree | e40d388e2b4b486998cd14c93a2382a0519e92c8 /plat/rockchip | |
| parent | 87aad73494c8980cf7511e65c99bcfc9f841990c (diff) | |
rockchip/rk3399: convert to for-loops to save code space
This converts two functions to use for-loops. This saves a bit of
space to help moving DRAM resume code to PMUSRAM.
Change-Id: Ie6ca490cf50c2ec83335cf1845b337c3e8a47496
Signed-off-by: Derek Basehore <dbasehore@chromium.org>
Diffstat (limited to 'plat/rockchip')
| -rw-r--r-- | plat/rockchip/rk3399/drivers/dram/suspend.c | 27 |
1 files changed, 13 insertions, 14 deletions
diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c index e892844e..608482ab 100644 --- a/plat/rockchip/rk3399/drivers/dram/suspend.c +++ b/plat/rockchip/rk3399/drivers/dram/suspend.c @@ -121,11 +121,12 @@ static __sramfunc void phy_pctrl_reset(uint32_t ch) static __sramfunc void set_cs_training_index(uint32_t ch, uint32_t rank) { + uint32_t byte; + /* PHY_8/136/264/392 phy_per_cs_training_index_X 1bit offset_24 */ - mmio_clrsetbits_32(PHY_REG(ch, 8), 0x1 << 24, rank << 24); - mmio_clrsetbits_32(PHY_REG(ch, 136), 0x1 << 24, rank << 24); - mmio_clrsetbits_32(PHY_REG(ch, 264), 0x1 << 24, rank << 24); - mmio_clrsetbits_32(PHY_REG(ch, 392), 0x1 << 24, rank << 24); + for (byte = 0; byte < 4; byte++) + mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 24, + rank << 24); } static __sramfunc void select_per_cs_training_index(uint32_t ch, uint32_t rank) @@ -139,19 +140,17 @@ static void override_write_leveling_value(uint32_t ch) { uint32_t byte; - /* - * PHY_8/136/264/392 - * phy_per_cs_training_multicast_en_X 1bit offset_16 - */ - mmio_clrsetbits_32(PHY_REG(ch, 8), 0x1 << 16, 1 << 16); - mmio_clrsetbits_32(PHY_REG(ch, 136), 0x1 << 16, 1 << 16); - mmio_clrsetbits_32(PHY_REG(ch, 264), 0x1 << 16, 1 << 16); - mmio_clrsetbits_32(PHY_REG(ch, 392), 0x1 << 16, 1 << 16); - - for (byte = 0; byte < 4; byte++) + for (byte = 0; byte < 4; byte++) { + /* + * PHY_8/136/264/392 + * phy_per_cs_training_multicast_en_X 1bit offset_16 + */ + mmio_clrsetbits_32(PHY_REG(ch, 8 + (128 * byte)), 0x1 << 16, + 1 << 16); mmio_clrsetbits_32(PHY_REG(ch, 63 + (128 * byte)), 0xffff << 16, 0x200 << 16); + } /* CTL_200 ctrlupd_req 1bit offset_8 */ mmio_clrsetbits_32(CTL_REG(ch, 200), 0x1 << 8, 0x1 << 8); |